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Type: Posts; User: oratie

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  1. Closed: Re: What does RLS Flow stands for in Physical Design?

    RLS - random logic synthesis
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    Closed: Re: Lockup Latch for DFT purpose

    We have two clock domains CLK1 and CLK2. The clock trees length (clock latency) are different in these domains. We did not balance them between domain (only balance inside each domain).

    During...
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    Closed: Re: Overwrite cell delay.

    It is possible to read a second liberty in multi-corner analysis. You have read different libraries (with different PVT) for the same cells. It allows analyze/optimize your design simultaneously in...
  4. Closed: Re: Can't Read SAED32nm libraries for design compiler

    Try such comand:

    set link_library "* lib1.db lib2.db ..."

    The character '*' in the list is important.
  5. Closed: Re: How do I know inbetween which pins do arcs exist in PrimeTime for timing libs?

    Try this command
    report_lib -timing_arcs tech_lib {AN2 OR2}
  6. Closed: Re: How to save PrimeTime command output into a variable in TCL?

    use "echo [get_object_name $p]"
  7. Closed: Re: Test and dft logic verification in flow and the lec

    DFT related logic (scan chain, scan_enable connection... are inserting during synthesis. It does not exist in RTL. So, LEC gate vs RTL will fail.
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    Closed: Re: TSMC 65nm Calibre dummy insertion tool

    LAYOUT PATH "/home/MD/Calibre/drc/TOPRETICULE.gds"
    LAYOUT PRIMARY "TOPRETICULE" - or what is the name of top cell inside your GDS file
  9. Closed: Re: Test and dft logic verification in flow and the lec

    These test and dft related logics are verified during ATPG (for example, by Synopsys TetraMax tool). Also, some kind of verification exist in Synopsys DFTcompiler (as a part of DesignCompiler).
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    Closed: Re: Post layout delay in cadence

    another way - create virtual clock and assign set_input_delay/set_output_delay for your ports related to this virtual clock.
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    Closed: Re: Post layout delay in cadence

    In Synopsys SDC there are commands set_max_delay/set_min_delay - they are for non-sync paths. Try them (or Innovus analogs) for constraining your combinational circuit.
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    Closed: Re: fifo with ram or flops

    The rams may be slower. If you have small fifo, the sram may be bigger, than FFs. It depends...
  13. Closed: Re: What does this mean in standard cell library?

    Units for index_1 is "time_unit". Units for total_output_net_capacitance is "capacitive_load_unit".

    The "1000, 1001, 1002, 1003, 1004, 1005, 1006" numbers are just fake numbers, the real indexes...
  14. Closed: Re: exclude certain clock from clock gating in DC_SHELL

    set_clock_gating_objects -exclude [all_registers -clock ...]
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    Closed: Re: Multi-vth design not performed

    if you have any scenarios defined, you should use set_scenario_option.
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    Closed: Re: Multi-vth design not performed

    Did you have set
    set_scenario_option -leakage_power true
    or
    set_leakage_optimization true
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    Closed: Re: .lib internal_power question

    If output Y switched due to changing input pin A - the power numbers are from the first table (related_pin=A).
    If output Y switched due to changing input pin B - the power numbers are from the...
  18. Closed: Re: Why do I get duplicate markers when loading and outputing a Calibre results datab

    Just a small advice: you can use "*drcCellName: 0" in your runset to get flat error database.
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    Closed: Re: Variable in Design Compiler for clock gating

    It is common in soft-IPs. Such clock-gating just switch-off clock for the whole block or the big part of the block (by using dedicated control ports). While the tool adds additional CGs for some...
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    Closed: Re: Variable in Design Compiler for clock gating

    It is common practice to have instantiated clock_gating cells in RTL, which control clock propagating for the whole big module.

    So, you need to use the following commans:
    identify_clock_gating...
  21. Closed: Re: is it correct to have filler cells being overlapped in floorplan b/w core and d

    You see overlapped cell because you have specified "-overlap_cell EMPTY1D". Without this option - no overlaps.
    Another question: is your IO library allowed overlapped cells? You should check...
  22. [SOLVED]Closed: Re: Common POLY layer in the digital standard cells

    Horizontal polygons of POLY have different datatype in the GDS file. It is marker layer "Cut-POLY".
  23. [SOLVED]Closed: Re: Synthesize an RTL from two technology .db files (of same node)

    You can mark particular cells with set_dont_use command.

    It's safely to have:
    set link_library "* $target_library other.db"
  24. [SOLVED]Closed: Re: Synthesize an RTL from two technology .db files (of same node)

    Yes, you can. Just specify both libraries in target_library of DC. (set target_library "aaa.db bbb.db")
  25. Closed: Re: How can you use Mentor Calibre to flatten a hierarchical DRC database?

    Try this DRC Runset option
    *drcCellName: 0
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