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Type: Posts; User: ptoo30

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    Closed: @DS2006A TSMC designkit

    please
    i need @DA2006A , TSMC 0.13um(RF and LOGIC) designkit
    i tried to develop designkit for @DS , but it is beyond my skill.
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    Closed: Re: How to generate less than 2ns impulse

    if peak voltage is small not several ten volt
    you can prepair odd number inverters and even number inverters
    then take AND
    if you use CMOS device for 130nm , the pulse width is around
    the...
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    Closed: Re: How to calculate W/L ratio for given current

    addition to upward guys opinion
    you may consider the variation caused from the etching error.
    you need the device data showing (1/(sq root W*L))
    and you need some effort to find proper L to keep...
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    Closed: Re: what is Dielectric breakdown

    its reliability issue. the fowler nordheim current pull the moving ion in sio2. and trap the ion. it causes current path in sio2. so voltage stressed to sio2 and time are some function of breakdown...
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    Closed: circuits under bond pads

    i do not suggest to use active area nor ESD circuit beneath pad. i only know the register was located beneath it on 2 um rule for LCD panel driver. but deep sub-micron process causes huge mechanical...
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    Closed: Re: "analog layout automation"

    analog design automation is not accomplished yet. as far as i know the optimiser was released but performance was poor. nec-not numerical electromagnetic code-has bipolar analog libraly. performance...
  7. Closed: sram hspice

    usually the leakage current of MOSFET is 1E-15A \depends on Vth swing channel length and width.
    so if u want to simulate 6T cell
    u have to make the fitting of spice parameter for sub threshold...
  8. Closed: Re: DRC Rule Question

    i think the reason why M2-M5 design rule is looser than M1 is ;
    even we use CMP, M2-M6 has some up and down beneath them.
    and M2-M5 are used for Vdd Vss considering reliability.
    for M1 thickness...
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    Closed: Re: What is matching report ?

    the meaning of matching is for MOSFET;
    mosfet beta is defined the channel L and W and Vth and oters when fabricating MOSFET , there is some difference between MOSFET even they are very closly...
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    Closed: Re: 90nm cmos models

    mosis can supply the design rule of IBM, but i donot know wheather they have S or SPICE paramter. anyway u can visit mosis site
  11. Closed: layout patterned ground shield

    i also think there is no automatic deign tool for ground shield.
    important item is to reduce the eddy current loss, for its simulation i use ADS or ASITIC:opensource aplying 3d electromagnetic...
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    Closed: Re: Level Shifting in CMOS

    the voltage gain of source folloer is less than 0dB because the out put voltage shall be devided by source resistance/( source resistance+1/conductance of MOS)
    but u can shink current so means...
  13. Closed: Re: pll design

    pll low jitter 1 to 3GHz
    i donot know the frequency so my thinking is correct or not for you?
    1 for cmos ic, use 2 inverters type osilator (in ADS you can find as saple)
    i experienced to...
  14. Closed: Re: DRC Rule Question

    m1 is lower level metal in the cell, we use m1 as interconnection between transistors so minimum line and space is needed.
    m2-m5 are interconnect between cells and do not need so small design rule....
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    Closed: Re: matching of two different capacitors

    the matching is affected from the thickness of oxide(nitride) , etching speed of x and y axis and circumstances of cell.
    i donot know the formula but the most precise etching i.e. design rule times...
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    Closed: Re: help on mos varactors

    my suggestion is based on only experience
    accumulation mode is;
    good for taking capacitance ratio uver 3
    good for 1Volt operation
    bad--capacitance absolute value depends on concentration of...
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    Closed: layout of rfic

    isolation shall be done this way
    using well you can make guardring
    if you use CMOS process this will help a little
    from TEG 20 micron well isolation makes 30dB 0.18u process
    (actual data,...
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    Closed: 0.2ohm resistor

    i think your bipolar process use copper wiring. use it for making 200mOHMregister. one suggetion is not to forget contact registance \\depends on process technology .. what is your emitter rule? how...
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    Closed: Re: ask for some questions in cmos vco design

    1 i am using MC7 for circuit design and ADS negative registance etc determination
    2 only for VCO design Tr parameter (SPICE and S-para) is needed. but one parts of total pll , VCO has many...
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    Closed: CMOS VCO design

    Looking for CMOS VCO design books(including circuits) or tools.
    Freq=1.5GHz Vdd=1.8v Kp=20MHz/v
    rgzs
  21. Closed: I think two reasons: 1 spice issue .tran...

    I think two reasons:
    1 spice issue .tran resolution usually spice decides it however nSEC area u may touch 0.1nS some preference affects resolution for examples the reltol shall be less than 1/100...
  22. Closed: modulator

    For 2.4g,it is common to use doublebalanced mixer(gilbert ). TDA6131xs is one of the solution.
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    Closed: layout soft

    cadence is better, others are no good for seamless design. as youknow, circuit design, layoutdesign and spice/rf-simulation are continuous ,each study will affect to next stage, some case result will...
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    Closed: without logic diagram some asumption will be...

    without logic diagram some asumption will be added to my suggestion. you need 27MHz cl and xcl. the one method is :
    1 multiply 27MHz to 54MHz using doubler(delay logic +nand gate)
    2 devide that...
  25. Closed: SSB noise usualy takes the unit dBc (ex. -100dBc)...

    SSB noise usualy takes the unit dBc (ex. -100dBc) at offset frequency of xx Hz from the ceter frequency.
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