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  1. Replies
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    Closed: Re: Rplpoly layout matching problem

    Case 1: You put in identical schematic values and you
    got (SDL synthesis) non-identical layout dimensions.
    This would seem improbable.

    Case 2: You got identical resistor segment geometries...
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    Closed: Re: Adaptive passes did not converge

    The error probably lies in specifying too many things that
    have a zero probability of coinciding. Although plain ol'
    convergence failures can also break a poorly-trapped
    optimization algorithm....
  3. Closed: Re: Operational amplifier driving capability test

    This looks like a CMOS op amp with a current limited
    output. You still need to decide whether you want the
    "ultimate current" (for reliability etc.) or the minimum,
    maximum current (for load...
  4. Closed: Re: Phase Interpolator for high frequency circuit

    "We"? I've done it (decade or more ago, 800MHz PECL
    clock recovery). Made 8 phases from the single incoming,
    with the non-quadrature ones by interpolation as you
    say (comparator, forget it -...
  5. Closed: Re: Operational amplifier driving capability test

    There are several output current measurements you might
    like, relating to different concerns.

    Many op amps (especially older medium-voltage bipolar ones)
    have explicit short circuit current...
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    Closed: Re: IRS25752 IC has no pin 1 marker

    The datasheet indicates to me that you are left to use
    the lot / date code on the top, or the mfr logo on the
    bottom, to orient yourself. See Pg 11.
  7. Closed: Re: Analog 16:1 MUX IC question, 4 vs 1 stage, transmission gate vs nmos

    I have worked on PMOS-only muxes, so a NMOS-only is not
    entirely insane. However you need to approach this from
    the application inward, specifically signal range and supply-set.
    This in itself...
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    [SOLVED]Closed: Re: AMS simulation of D-FF

    The module has no reset and no special-case initialization code,
    so there will be some problems getting an initial solution.


    Here's code for a well-used veriloga DFF from a CMOS standard
    cell...
  9. Closed: Re: Extracting energy from gyroscope precession

    There are certainly gyroscopes which are motorized to keep
    them spinning (look in any inertial measurement unit prior to
    2000-ish fielding; optical and MEMs "gyros" are late to the
    party).
  10. Closed: Re: What is the conditions for complementary BJTs

    Depends on whether you're talking IC design (run what
    ya brung) or PCB design (shop 'til you drop).

    A complementary bipolar process development would aim
    for things like roughly-equal Vbe@Ic...
  11. Closed: Re: What is the difference between BVDSS and BVDS

    That would be something like BVdb_ but this is often not
    specified separately (especially if the foundry knows that
    lateral punchthrough or hot carrier reliability degradation
    happens well below...
  12. Closed: Re: Verilog-a code to latch analog voltages

    https://designers-guide.org/verilog-ams/index.html
  13. Closed: Re: Cadence Virtuoso - Border sheet locking / move to background

    You could also "take that A3 sheet private", and add a small
    instance/dwg rectangle as a "selection handle" (like maybe
    just around the title block) and then the sheet symbol will
    only be...
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    Closed: Re: Donors , Acceptors and Traps

    Impurities may or may not be trap sites.

    Dopant is desired to be substituted fully into the lattice
    and then it becomes electrically active (in a good way).
    Semiconductor properties are about...
  15. [SOLVED]Closed: Re: Do The Input And Output Capacitors Effect Efficiency In Switching Regulators

    Input filter capacitor ESR is a big deal in low voltage
    POL buck converters. The capacitor sees current
    equal to IOUT - charging during output switch "off"
    interval and discharging during "on"...
  16. Closed: Re: Help on Ocean scripting: run one analysis and use that results in another

    Can't help you with Ocean but used to do this a lot in
    cdsSpice, never could get the hang of it in bare Spectre
    or Ocean.

    But basically I'd make up a simple data structure (for
    example,...
  17. Closed: Re: Factors deciding Silicon Wafer Thickness

    Thinning (EOL) is needed more than before, for some of
    the low profile packaging that's become popular (not to
    mention 2.5D/3D integration). People are also doing
    extreme thinning to get...
  18. Closed: Re: Installing Cadence , Assura , EXT and MMSIM in Ubuntu

    I think you may only find a choice between various "seams"
    at which stuff falls apart.

    Ubuntu is great for people who don't want to mess with
    graphics setup. RHEL / CentOS didn't give me much...
  19. Closed: Re: Deaign of low ON resistor CMOS transmission gate

    If you care about things like charge injection then you may
    be forced to make D-G, S-G overlap capacitances equal and
    then you're also stuck with equal W and have to adjust the
    NMOS L for ohmic...
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    Closed: Re: Exact resistance output?

    If the resistance desired is "end to end" and the e-pot likewise
    (that is, not a shunt-to-ground or something like that) you could
    go for a higher bit count e-pot, or you could cascade two very...
  21. Closed: Re: Metal Oxide Semiconductor in strong Inversion

    Before we go any further, how about you quantify:


    "fast" and "slow" sweep time for a C-V measurement
    on normal equipment such as shown


    minority carrier lifetime in bulk regions
  22. Closed: Re: Metal Oxide Semiconductor in strong Inversion

    When you say "at the interface" it appears you assume that
    these are all carriers sitting in bulk silicon, leaning up against
    the wall just smoking a cigarette and pretty much free to do as
    they...
  23. Closed: Re: Metal Oxide Semiconductor in strong Inversion

    I believe you're looking at charge pumping C-V for the
    purpose of quantifying the trap density.

    The "frequency" high or low pertains to the trap lifetime
    (reciprocal). There are all kinds of...
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    Closed: Re: Switching power supply

    If you want all of those voltages from a single switch
    and single core you will see cross-regulation as an issue
    (one winner, N "also-rans").

    If you are in it for amusement / education, then...
  25. Closed: Re: How is the maximum inductor value in a technology process is determined

    One limit is the series resistance of the spiral, and
    somebody in the foundry design group might pick
    a number from an unspecified orifice and declare
    it a limit.

    If you need Q then you're...
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