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Type: Posts; User: dave_59

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  1. Closed: Re: Creating Verilog wrapper around a system Verilog DDR4 memory model from micron

    You can use port declaration expressions.


    module ddr4_module_wrapper(
    input .CK(ddr4_bus.CK),
    ...
    inout .DQ(ddr4_bus.DQ),
    ...
    );
  2. Closed: Re: Verilog/SV: can assign + ternary produce latches?

    This is one of the reason SystemVerilog has always_comb, always_latch, always_ff - to show and check your intent
  3. Closed: Re: what is the difference of creating object inside initial block or outside block

    That is not correct. In both cases, a class object gets constructed and gets assigned to the static variable h, which is globally available through hierarchical references.

    You won't see any...
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    Closed: Re: Reset Value using a parameter

    I'm sure. Verilog (and thus SystemVerilos) implicitly extends or truncates the width of the RHS of a procedural assignment to match the LHS.
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    Closed: Re: Reset Value using a parameter

    There's no need to size the parameter. Verilog/SystemVerilog always pads 0's implicitly.

    parameter RESET_VALUE = 5;
    logic [WIDTH-1:0] data;

    always_ff @(posedge clk)
    if (~reset)
    data...
  6. Closed: Re: The difference between | operator and keyword or

    The only place the or keyword is allowed is inside an event expression to say wait for this event or that event.

    always @(a or b) ...
    always @(posedge clk or negedge reset) ...

    This is in...
  7. Closed: Re: Preferred shell for scripting, csh or bash?

    Although perl/python are interpretive languages, thay are not interactive like a shell. You still need shell scripts to setup your environment, create directories, and execute your perl/python...
  8. Closed: Re: System Verilog error VLOG-13069 from Questasim with unpacked array

    Verilog/SystemVerilog only allows contiguous slices of arrays. Your original question seems like you were trying to take a noncontiguous slice, but then your updated example was definitely...
  9. Closed: Re: System Verilog error VLOG-13069 from Questasim with unpacked array

    You have the select indexes in the wrong order. Packed dimensions come after unpacked dimensions.
    slice=bt1[1][12:8];
  10. Closed: Re: Using generate and for loop to index signal name

    You cannot iterate over identifier names. The best you could do is

    wire in[N-1:0] = {..., in3,in2,in1,in0};

    In SystemVerilog, this can be simplified as
    alias in = {..., in3,in2,in1,in0};
  11. Replies
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    Closed: Re: SystemVerilog Interface signal assignment

    A quick improvement is getting rid of the intermediate assignments using


    assign out = Myif1.out | Myif2.out ;



    As you have discovered, interfaces work best is you can keep connections...
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    Closed: Re: External C++ compilation and DPI question

    Try
    g++ -c -I<install_dir>\questasim\include mytest.cpp
    g++ -shared -Bsymbolic -o mytest.dll mytest.o -L<install_dir>\questasim\win32
  13. Replies
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    Closed: Re: External C++ compilation and DPI question

    Why do you have that requirement?
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    1,051

    Closed: Re: External C++ compilation and DPI question

    If you are using a version of Questa/Modelsim within the last 8 years, you can put the C/C++ file on the vlog command line and skip the separate gcc step.
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    Closed: Re: Logic duplication and optimization

    Common subexpression elimination is a common optimization found in both software and hardware tools. You shouldn't have to write your code to help the optimizer.

    That said, you should write your...
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    Closed: Re: is accellera UVM free?

    It's released with the Apache 2.0 license

    You can find information about using it here.

    Although there are ways to run some UVM code freely, commercial projects need commercial software to...
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    Closed: Re: default statement in case

    The default case branch is there to prevent your FSM from locking up unto an unspecified state. In simulation, this can happen when X's get into your state variable. For synthesis, you want your FSM...
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    Closed: Re: Testbench input stimulus

    You may have race conditions if your module also has code that waits for @(posedge clock). The same rules apply between your testbench and module as well as module to module. Use non-clocking...
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    Closed: Re: parameterized insertion of bits to data

    I don't understand either.
    Please show an example with sample data input and output values. How is control used? What order to the bits in append_data get selected? What happens when bits_to_append...
  20. Closed: Re: Alternative of “can not set both range and type on function declaration” in veril

    Remove the reg keyword in the function return.
  21. Closed: Re: Req: Bluspec Systemverilog good learning materials

    http://wiki.bluespec.com
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    Closed: Re: Beginning and end of a time step

    You are missing the code that changes clk and in. And nothing changes at the end of a time step. Change has to happen first, and only when there are no more changes can you proceed to the end of the...
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    Closed: Re: Beginning and end of a time step

    You have to look at how every signal changes value. Assuming every signal that changes on a clock edge uses a non-blocking assignment, there will be no race conditions. And you may have to look...
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    Closed: Re: Beginning and end of a time step

    If you use blocking assignments to a and b, you have a race condition. That is the whole point of using non-blocking assignments when one always process writes, and another always process reads the...
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    Closed: Re: Beginning and end of a time step

    This is not the correct way of thinking about it. The RHS of non-blocking assignment gets evaluated as soon as the previous statement completes. The LHS c gets scheduled to update after in another...
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