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  1. Closed: Re: Problem implementing project in ISE 14.5 using ipcore fifo_generator 9.3

    the truth is that the project was done in Vivado 2017.3 for a virtex-7 and I am trying to adapt it for a virtex-5, but I am a novice in ISE. I just saw the Virtex-5 FPGA User Guide datasheet (p. 370)...
  2. Closed: Re: Problem implementing project in ISE 14.5 using ipcore fifo_generator 9.3

    thanks for the help ads-ee ... tell you that ISE coregen creates the XCO file, which I could add to my project and solve that error with ipcore, but now I am having a similar error in another module...
  3. Closed: Problem implementing project in ISE 14.5 using ipcore fifo_generator 9.3

    Greetings ... comment that I am with a small project in ISE 14.5, I have managed to synthesize but I am having compatibility problems with the ipcore fifo_generator 9.3 when implementing and I am...
  4. Closed: Help with the simulation in Modelsim using ISE 14.5 and simulation code SystemVerilog

    Greetings ... a couple of days ago I have been spending a project done in Vivado 2017.3 to ISE 14.5, because it is required to adapt it to a Virtex5 device. So far I have managed to adapt it and be...
  5. [SOLVED]Closed: Re: problem moving from SLL to shift_left in ISE 14.5

    Thanks for the help ... I tell you that I was able to solve my problem, removing all these operations from OR and SLL, leaving these lines as follows.



    library IEEE;
    use...
  6. [SOLVED]Closed: problem moving from SLL to shift_left in ISE 14.5

    Greetings ... tell you that a couple of days ago I am going through a VHDL project made in Vivado 2017.3 to ISE 14.5. Several of these sources had vhdl 2008 syntax that ISE does not recognize, I...
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    [SOLVED]Closed: Re: Problema para crear coregen en ISE 14.5

    thanks for all the help adds-ee, I commented that I solved my problem ... the version I had downloaded from ISE consisted of a compressed file with the complete installer, but there is also an...
  8. Replies
    4
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    405

    [SOLVED]Closed: Re: Problema para crear coregen en ISE 14.5

    I am using the Systema Edition but as you say the license I use for Vivado may not work with ISE. What can I do in this case?
  9. Replies
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    405

    [SOLVED]Closed: Problem creating coregen in ISE 14.5

    Greetings ... a couple of days ago I am trying to take a project that was done in Vivado 2017.3 to ISE 14.5 since it is required to implement it on a Virtex-5 device. This project includes some IPs...
  10. Closed: Re: How to create an IP core based on a project in ISE?

    thanks dpaul ... excuse me how can you create the .ngc file in ISE? I do not find specific information.
  11. Closed: How to create an IP core based on a project in ISE?

    Greetings ... a couple of days ago I have been doing a project in ISE 14.5 and for this I need to create an IP that is based on a small project (programmable clock) that I have also implemented in...
  12. [SOLVED]Closed: Re: Send one parameter from systemverilog to another in Vivado 2017.3

    Thanks for the help ... tell them that I managed to solve my problem, where I only send the time parameter as follows.

    stimulus.sv


    local_g1_test_bench #(.sim_pim1_uclk (2500))...
  13. [SOLVED]Closed: Re: Send one parameter from systemverilog to another in Vivado 2017.3

    Thanks dpaul for responding, when making this change I am sending the differential clock as shown in the following code.



    `timescale 100ps/100ps

    module stimulus();
    ...
  14. [SOLVED]Closed: Send one parameter from systemverilog to another in Vivado 2017.3

    greetings ... tell you that I am very new to systemverilog and I have some files to perform a simulation test for a project. This test has a main file stimulus.sv which creates an instance of another...
  15. Closed: How I can make use of the resources of only certain regions of the device in Vivado?

    Greetings ... tell you that a few days ago I translated a single verilog file to vhdl to add it to my vhdl project in Vivado 2017.3 which has the function of controlling the transmission and...
  16. [SOLVED]Closed: Re: Error: Subprogram does not have a body when creating vhdl packa

    I just fixed it, I wasn't getting it very much. This is my new code.


    BIBLIOTECA ieee;
    USE ieee.std_logic_1164.all;
    USE ieee.std_logic_unsigned.all;
    USE ieee.std_logic_misc.all;
    USE...
  17. [SOLVED]Closed: Re: Error: Subprogram does not have a body when creating vhdl packa

    Thanks for answering ads-ee ... I'm not sure what you mean by "indexed" name is not a type.
    I have made some changes based on the data sheets...
  18. [SOLVED]Closed: Error: Subprogram does not have a body when creating vhdl package.

    Greetings ... comment that I am new creating vhdl packages and a couple of days ago I am trying to create one, but I am having the following error shown in the image.

    156119

    Can someone please...
  19. Closed: Re: What is the vhdl equivalent of "initial begin" to initialize a ROM.

    Thanks for answering FvM, tell you that S1_CLKOUT0_FRAC_EN or S1_CLKOUT0 if they are parameters and S1_CLKOUT0_FRAC_A and others are signals that I had to create since I could not make a direct...
  20. Closed: What is the vhdl equivalent of "initial begin" to initialize a ROM.

    Greetings ... tell you that a couple of days ago I am trying to translate a verilog file to vhdl and I found the next block that initializes a ROM.



    // Make sure the memory is implemented as...
  21. Closed: Re: Problem calling a function from my vhdl project in Vivado.

    Thanks for the help. Is there a rule for this type of verilog syntax for vhdl? because the examples are not clear to me. Tell you that I did the translation based on the following link...
  22. Closed: Problem calling a function from my vhdl project in Vivado.

    Greetings ... comment that a couple of days ago I am trying to translate an .h file to vhdl, this in order to be able to use the functions in my vhdl project. The truth is that I am new doing...
  23. Closed: Re: Help to make use of an .h file in my vhdl code

    Ok, thank you very much for the help
  24. Closed: Re: Help to make use of an .h file in my vhdl code

    Okay, if there is no other way, I will start translating my .h file to vhdl.
    Another question I have is the use of "initial begin" in verilog. Is there any equivalent in vhdl for this?
  25. Closed: Re: Help to make use of an .h file in my vhdl code

    When I include it directly, it gives me the following error shown in the attached image.

    155732
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