Search:

Type: Posts; User: timof

Page 1 of 20 1 2 3 4

Search: Search took 0.01 seconds.

  1. Replies
    1
    Views
    195

    Closed: Re: Question Regarding Max Current Per Width

    Normally, every technology provided by the foundry (and definitely - 180nm from TSMC), comes with rules for current densities for electromigration.

    These rules are described in electrical deign...
  2. Closed: Re: IC tape-out with TSMC - export license required?

    This is something that should be discussed with an export control lawyer, not at the discussion board.
    What if someone says "yes", or says "no" - would you follow that direction based on such an...
  3. Closed: Re: How to choose optimal wire width of spiral coil to attain high q factor?

    All major vendors of EM analysis tools - Integrand (EMX), Helic (VeloceRF), Lorentz (PeakView) - provide tools to synthesize an inductor layout to desired characteristics (L, Q, ...).
  4. Replies
    2
    Views
    399

    Closed: Re: Properties of MIM capacitors

    There are tons of data on MIM capacitors in the literature - check this paper, as an example, and its citations:

    J. A. Babcock et al., "Analog characteristics of metal-insulator-metal capacitors...
  5. Replies
    2
    Views
    459

    Closed: Re: Understanding LVS results (hierarchical)

    The ports on the layout are defined by text labels "attached" to port/pin text layers.

    Normally, the ports are defined at the top level only.

    There is a command in Calibre (involving "TEXT...
  6. Replies
    2
    Views
    393

    Closed: Re: Two polysilicon layers for gate connection

    If there are many metal layers in a process (let's say, 10 or 15), lower metal layers are thin and highly resistive, and upper metal layers are thick and low resistive.
    That's why top metal layers...
  7. Replies
    4
    Views
    523

    Closed: Re: Semiconductor software simulation

    https://tcad.com/Software.html
  8. Closed: Re: Temperature mobility degradation factor (c) - MOSFET SOI

    Any textbook on semiconductor physics will have something on this topic.

    Or you can look it up at Wikipedia:

    https://en.wikipedia.org/wiki/Electron_mobility

    Check the section on "Temperature...
  9. Closed: Re: Temperature mobility degradation factor (c) - MOSFET SOI

    This is an empirical equation or model, describing a temperature dependence of carrier mobility.
    Mobility decreases with temperature, that's it.
    "C" is a fitting parameter, that hsould be found...
  10. Closed: Re: Lectures or textbooks related to high-speed wireline circuits and systems?

    How about this:
    ...
  11. Closed: Re: [moved] Value of lateral electric field(E0) in UMC 65 technology

    Lateral electric field in a MOSFET is not constant, it has a sharp peak near the drain.
    But I doubt that such a deep microscopic characteristic, even if known, would be used in an empirical...
  12. Replies
    6
    Views
    1,353

    Closed: Re: Biasing an array of current steering DACs

    And even within one DAC, make sure that the voltage drop along the ground net, feeding the current sources, does ot create too large Vgs mismatch across current sources.
  13. Replies
    3
    Views
    1,359

    Closed: Re: Cannot generate calibreview pop-up after PEX

    OK, thanks.
    Indeed, some problems go away after you restart Virtuoso.
    It's probably the first thing to try, when debugging such problems.
  14. Replies
    3
    Views
    1,359

    Closed: Re: Cannot generate calibreview pop-up after PEX

    Why do you need a pop up window?
    If you selected Calibre View as output post-layotu netlist format, the extraction tool should just generate it. Check your directory, for the presence of this file.
  15. Replies
    6
    Views
    699

    Closed: Re: DAC unit cap selection for SAR ADC

    A high attention should be paid to wiring parasitics - which may destroy your matching / binary weighting of the capacitors in the capacitor bank.
    Use field solver (built-in in all standard...
  16. Replies
    5
    Views
    648

    Closed: Re: Polarization MOSFET SOI

    In FDSOI technologies, adaptive back bias (voltage applied to substrate or well under BOX) is a popular and common technique to control leakage vs performance tradeoff.
    Positive voltage will lower...
  17. Replies
    5
    Views
    648

    Closed: Re: Polarization MOSFET SOI

    Questions:

    1. What do you mean under "polarized" - applied voltage, or doping type? (I think, you mean the former).
    2. What do you mean under "bulk" - body of SOI MOSFET, or substrate region...
  18. Replies
    1
    Views
    297

    Closed: Re: TSMC65nm CRN65LP PDK Calibre and PEX Issues

    This post at Mentor Communities webpage may help you:

    https://communities.mentor.com/thread/10952

    This post gives some pointers to the documentation, and explains the idea and flow.

    The...
  19. Closed: Re: How to measure the C parasitic (internal capacitance) of an inverter using Spectr

    I agree that circuit simulator cannot be used to do parasitic extraction (calculation of parasitic elements - R, C, etc.) - there are specialized tools for that (parasitic extractors - such as...
  20. Closed: Re: How to measure the C parasitic (internal capacitance) of an inverter using Spectr

    Parasitic elements (R, C, L, K) have the same relationship with the circuit simulator as design elements - transistors, diodes, etc.
    Their characteristics are determined by their structure (width,...
  21. Replies
    4
    Views
    468

    Closed: Re: Voltage drop of on die power gating cells

    I would think the effect of voltage drop on power switches on timing would be the same as the effects of voltage drop on the interconnects (external and virtual power / ground nets).
  22. Closed: Re: How to measure the C parasitic (internal capacitance) of an inverter using Spectr

    From the diagram, Cpar=Cw is parasitic capacitance of the wire (more accurately - parasitic capacitance of the net).

    In distributed RC parasitic extraction Cpar may correspond to a large number of...
  23. [SOLVED]Closed: Re: Errors occurred after setting up calibre view

    Looks like a problem caused by the syntax - by the angular brackets.
    Try replacing them by square brackets.
    Different tools have different requirements on brackets (e.g. triangular vs square), and...
  24. Closed: Re: Synopsys Custom Designer; simulation error for LPE in Inverter cmos circuit

    This might be a problem.
    This DSPF file is valid, but nets VSS and VDD extracted as ideal nets - meaning they are represented as one node, with no parasitic resistors.
    I suspect the command in...
  25. Closed: Re: Synopsys Custom Designer; simulation error for LPE in Inverter cmos circuit

    Good, the .SUBCKT statement looks good.
    You can also check *|NET section for nets VDD and VSS, to make sure these nets are extracted correctly - and you can then assume that the extraction went...
Results 1 to 25 of 500
Page 1 of 20 1 2 3 4