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Type: Posts; User: amarnath

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  1. Closed: Re: LDO's PSRR

    PSRR is a function of the loop gain (Aopenloop*Beta). So it can be maximized by increasing loop gain.
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    Closed: Re: low drop out voltage regulator

    Just search for middlebrook's method. Connect a very big inductor from the feedback node back to your opamp input (its a dc short and ac open circuit) . add an ac voltage source to your input 1 v AC...
  3. Closed: The curvature of my BGR output is wrong. Why?

    I think your ctat component is more inherently. What correction are you trying to do ? is it second order?


    Amarnath
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    Closed: About Charge Pump and VCO

    http://www.geocities.com/fudinggepll/index.html

    http://www.geocities.com/fudinggepll/PLLProj.pdf


    First link takes you to the page , the second is the link to the document on PLL's which i...
  5. Closed: Why for Charge Pump they do Phase Noise analysis??

    You do it so that you can asess how much of the phase noise is contributed by the charge pump to the output clock.


    amarnath
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    Closed: How to select charge pump current?

    Yes i understand, thats why i said it all depends on what application the PLL is going to be put to use to. For lower end applications it may not matter as much, but it is good to understand what...
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    Closed: charge pump

    which charge pump do you mean a voltage charge pump to pump up the voltage or the one used in PLL's/


    amarnath
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    Closed: choosing a charge pump current

    wn=sqrt(ip*kvco)/(2*pi*N*C1).Fit in the other parameters like divider ratio, gain of the VCO and the loop filter capacitor. Overall the pump current is chosen based on noise requiremtns ,BW,lock...
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    Closed: ring oscillator frequency variation

    yes you need to use trimming to trim the frequency across corners. But variation across V-T can also be high enough, but atleast you can remove the variation across process by having sufficient...
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    Closed: About Charge Pump and VCO

    Hi Mouzid, please do a google search for "Fuding Ge pll thesis"

    There you will get this thesis. Yes the loop filter needs to be designed so that the PLL locks to the input frequencies.You will...
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    Closed: Reducing ripples in VCO

    to reduce the ripple on the control voltage size the capacitor to filter the ripple.In a second order loop filter the second pole should be sized to filter out the ripple.
  12. Closed: DLL based Frequency Multiplier for PCS application

    He means , he is going to generate multiple phases and then using these phase he could double or quadruple the input clock frequency.


    amarnath
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    Closed: static phase offset PLL

    in any feedback system the output settles to some value within some error % difference compared to the input. This error reduces but cannot be eliminated, it is less in case of second order PLL.

    ...
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    Closed: Frequency Compensation

    The resistor nullfies the zero if its sized such that it cancels out the zero created by the miller cap. The resistor can also be sized to move the zero to the right half plane to increase the phase...
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    Closed: Frequency Compensation

    Just add a miller cap as in a two stage opamp, this will introduce a zero since you now create another path for the signal to reach the output.Then try moving this zero to the right half if needed to...
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    Closed: How to predict the locking time of a PLL?

    Iam talking about an approx expression for a PLL using a second order loop filter(two caps with a resistor in series with one cap).This is the approx expression you get once you make some...
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    Closed: high speed comparator/opamp means what??

    speed of the comparator depends on how much current you give the comparator so that the capacitors at the output of the opamp can charge/discharge as soon as possible, this is also a measure of the...
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    Closed: How to predict the locking time of a PLL?

    lock time of an integer N PLL is approximately given 4/FB ,where FB is the loop bandwidth of the PLL.


    AMARNATH
  19. Closed: Why vil and vih has to be calculated through dc sweep ??

    yes dc sweep is the best way, i just told you an alternative to dc sweep and also a method by which your transient result can match the result of your dc sweep.


    amarnath
  20. Closed: Why vil and vih has to be calculated through dc sweep ??

    depending on the step size in the tran analysis, the values will be calculated at each step, so the vil vil values will yield more accurate results than when the step size is large.hope its clear.
    ...
  21. Closed: Why vil and vih has to be calculated through dc sweep ??

    iam talking about the transient step size not the ramp step size..
  22. Closed: Why vil and vih has to be calculated through dc sweep ??

    you can do the same thing through transient sweep also but keep the step size as small as possible.


    amarnath
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    Closed: ring oscillator problem

    what is the supply voltage. the oscillator should oscillate from vdd to vdd-ir, where r is the resistance of the load of the delay element.i is the current when full switching occurs .

    amarnath
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    Closed: Layout Tools

    compactor uses algorithms which are used to decrease the area of the custom layout. but mostly layouts done by experienced layout guys is always better than anything done by an algorithm.

    ...
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    Closed: How to decide PLL LoopBandwidths?

    http://www.geocities.com/fudinggepll/PLLProj.pdf
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