Search:

Type: Posts; User: hcu

Page 1 of 4 1 2 3 4

Search: Search took 0.28 seconds.

  1. Closed: Re: How to fix a setup violation /hold violations in net-to-net path ??

    the question posed to me is, how to fix setup violation ? my answer is to reduce the combinational path delay sitting in between Lflop and Cflop.
    the next question is, how you do that ? my answer...
  2. Closed: Re: How to fix a setup violation /hold violations in net-to-net path ??

    the .rpt file that comes after the command "report timing -num_paths 3000 > timing.rpt" during synthesis. From the textbooks what i came to know is, net-to-net violations is addressed using...
  3. Closed: Re: How to fix a setup violation /hold violations in net-to-net path ??

    Have you not seen any "net to net " timing path violations in the timing reports.?
  4. Closed: Re: How to fix a setup violation /hold violations in net-to-net path ??

    I am looking into STA theory. why you ignored IN-OUT path.?

    In the attached picture , I am talking about path-no 4 .

    And how to fix violations for the paths which is through a combinational...
  5. Closed: How to fix a setup violation /hold violations in net-to-net path ??

    Hi,


    1.)why INPUT-to-OUTPUT path in sta is considered as a combinational path (not as both comb and seq) even though u see one launching flop and capture flop in between these ports ??

    2.)how...
  6. Closed: Driver implementation for a modular SG DMA IP of Altera FPGA ?

    Hello,

    This question correctly relates to this thread, I believe

    I am writing a driver c code for altera fpga modular scatter gather DMA. where i have to decide the number of descriptors (that...
  7. Closed: Ref. design of S10 with a PCIe enabled 256-bit bursting slave interface (HPTXS) Port

    Hello all,

    please suggest me a reference design on stratix 10 board with a PCIe , enabled high performance burst interface (HPTXS) port of 256 bit width.
    I searched on the net to have a clear...
  8. Closed: Re: pcie system on startix 10 board, crashing the harddrive of host system ??

    refclk port of pcie is given 100 Mhz. and the clock out from this pcie is 250Mhz.

    refclk is connected to AK40 and refclk(n) is connected to AK41. (motherboard reference clock)
    Thanks for the...
  9. Closed: Re: pcie system on startix 10 board, crashing the harddrive of host system ??

    will this work because im using pcie core clock (default 250 Mhz) supplying to all other IP components. (no other clock sources used).
  10. Closed: Re: pcie system on startix 10 board, crashing the harddrive of host system ??

    yes, 2x4 power connector is unused. Only pcie slot is connected. Then atleast i should able to access the OCM from the nios atleast , right ?. But im getting "download elf failed".

    we actually do...
  11. Closed: pcie system on startix 10 board, crashing the harddrive of host system ??

    Hello,

    This is the SoC integration targeting for S10 board. For some reason , after programming .sof file on the board and trying to run simple hello_world program in eclipse sdk. I endup with...
  12. Closed: Configuring BARS and SIZE in Avalon-MM Stratrix 10 Hard IP for PCI Express bars ??

    Hello all,

    I am working with altera s10. I have some experiments which are ,

    exp 1: IP's are My own logic, pcie , OCM ,emif (DDR3)
    here OCM is mapped to bar0 and emif is mapped to bar2 , both...
  13. Closed: IS this IP integration of ddr3 and pcie gen3 and nios 2 correct ?

    Hello all,

    I am new to this altera stuff started working on s10 device.

    I am showing you a screenshot consists of
    1. Hard IP of pcie gen3 for s10
    2. onchip mem
    3. nios 2 processor
    4. jtag...
  14. Replies
    4
    Views
    680

    Closed: Re: Is sGDMA integration correct in this SoC ??

    I am looking for a template of dma controller c file and want to use it. Yes i know , xilinx sdk have a inbuilt example dma code where i used to call ...init() function and a...
  15. Replies
    4
    Views
    680

    Closed: Re: Is sGDMA integration correct in this SoC ??

    I pressed the button, it is success . but don't know how to proceed further. I want a working C code.
  16. Replies
    4
    Views
    680

    Closed: Is sGDMA integration correct in this SoC ??

    Hello all,

    I am using modular scatter-gather DMA core to transfer data from my custom IP: custom_design_32_0 to other custom IP: custom_design_32_1 on the stratix 10 development board.

    I want...
  17. Closed: Unable to do data transfers with altera DMA controller.

    Hello all,

    I am a beginner just started working on altera fpga devices . I have designed an SoC (see figure) where it has NIOS II , onchip_memory1 and onchip_memory2 ,altera DMA controller and...
  18. Closed: Re: From where I can download GNU gcc 4.3.3 version of compiler for windows?

    Thanks for the cygwin help !! this website speaks the same (( ref link:http://preshing.com/20141108/how-to-install-the-latest-gcc-on-windows/))

    i installed it and tried the command
    wget...
  19. Closed: Re: From where I can download GNU gcc 4.3.3 version of compiler for windows?

    145487

    I found the links as i shown you in the picture. let me know , Is these top two tar.gz and tar.bz2 is sufficent ? And these are really made for windows OS ? .how can i untar them. im not a...
  20. Closed: Re: From where I can download GNU gcc 4.3.3 version of compiler for windows?

    yes, its a old version. For compatibility with the other tool in my PC. i was recommended GNU gcc 4.3.3 as per the documentation.
  21. Closed: Re: From where I can download GNU gcc 4.3.3 version of compiler for windows?

    I think your answer suits for linux .Ofcourse this is a "LInux Software " . but iam looking for windows software.
  22. Closed: From where I can download GNU gcc 4.3.3 version of compiler for windows?

    hello all,

    I want a gcc 4.3.3 compiler files for a windows machine. i have done googling but not found the required version. even if i found ,there are archives with different file sizes with...
  23. Replies
    3
    Views
    1,087

    Closed: Re: doubt on this simple verilog pipeling

    thank you,

    I learn a point from the Point A ,you mentioned.


    coming to point B, yes,i not pipelined vld and opcode. but from the waveform at 150ns data_temp(register) already holds the value b...
  24. Replies
    3
    Views
    1,087

    Closed: doubt on this simple verilog pipeling

    Hi all,


    // Code your design here
    module data_sampling_doubt1 (
    input clk,
    input rst,
    input [3:0] data_in,
    input vld,
    input [1:0] opcode,
  25. Closed: Re: Synopsys Design Compiler - Ungroup Synthesized Designs

    Use bottom-up approach . it will certainly help you.
Results 1 to 25 of 93
Page 1 of 4 1 2 3 4