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Type: Posts; User: dpaul

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    Closed: Re: Transferring data from PS to PL

    see this thread on PS-PL communication - https://forums.xilinx.com/t5/Embedded-Processor-System-Design/PS-PL-communication/td-p/847775

    You might also need:...
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    Closed: Re: Transferring data from PS to PL

    For PL to PS, you can also use the AXI i/f.
    The PS section can typically stay as the master and the PL section can stay as the AXI slave.


    The AXI master side (PS) needs to initiate a write...
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    Closed: Re: verilog code using vivado

    Post the complete RTL.
    Are you properly doing the system clock input pin assignment in the xdc file?
  4. Closed: Re: Verilog code for 8 bit register with read/write

    I hope you realize that in order to have data from an axi slave to a 8 bit register, the 8 bit register must also have an axi wrapper. That axi wrapper must act as an axi master. Since you already...
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    Closed: Re: Embedded Linux Application

    For Xilinx FPGAs containing ARM core/s I can recommend you to start with the this free to download eBook:
    http://www.zynqbook.com/

    Many of the answers you can get there.
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    [SOLVED]Closed: Re: Modelsim clock signal

    I would never use stuff as create_wave or try to force a toggle behavior in order to generate a fundamental signal such as clock.
    For signals such as clocks and resets, drive them from the...
  7. Closed: Re: Verilog code for 8 bit register with read/write

    There are numerous axi slave example codes in the net which can be re-used to suite your purpose. Have you tried them?

    If you have trouble understanding the protocol, see this vdo -...
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    Closed: Re: dft-how to use .bench format

    Seems that some people are working with .bench files in the same time frame.
    Similar post in the Xilinx forum: https://forums.xilinx.com/t5/Design-Entry/bench-file/m-p/997165#M21159

    I think that...
  9. Closed: Re: Attempting to get a license for feature 'Synthesis' and/or device 'xcvu440'

    Adding the ads-ee comments from above....
    Xilinx ISE is for Series6 and previous versions of FPGAs.
    If your target FPGA has changed, so should your Xilinx tools also.

    I am pretty much sure...
  10. Closed: Re: Issues during attemp of implementation of "Matrix multiplification" Verolig proje

    Yes, use Core Generator to generate.

    Otherwise consult the Xilinx ISE Synthesis guide in which there probably are RTL templates which infer BRAM.
  11. [SOLVED]Closed: Re: Request for clarification: multiplication and hardware multipliers blocks

    Read the UG901 first.

    Using the operator * will infer the DSP48 block (not sure if it is also DSP48 for Spartan3, but will be a similar block). However if you still want to be sure, use the...
  12. [SOLVED]Closed: Re: Request for clarification: multiplication and hardware multipliers blocks

    Yes the internal MUL block of the FPGA will be inferred.
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    [SOLVED]Closed: Re: vivado post route simulation problem

    The OP finds a mismatch b/w func sim & post-impl sim. I found out he has no constraints file and still performing post-impl sim. Is it correct to perform a synth & pst-impl sim without design...
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    Closed: Re: Help in understanding innovus

    innovus tool should have a user reference manual, you can refer there for details.
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    [SOLVED]Closed: Re: vivado post route simulation problem

    Your synth log says there are no timing constraints for your design.
    What are you trying to do?
  16. Closed: Re: Verilog wire vs reg. Which one should I use and when / why?

    Yes I meant that.
  17. Closed: Re: Verilog wire vs reg. Which one should I use and when / why?

    A reg used inside an always block leads to the inference of a flop. You use it when you are defining sequential logic.

    When you are writing RTL for combinatorial logic, something outside the...
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    [SOLVED]Closed: Re: vivado post route simulation problem

    That's doesn't look like the complete synth log file.
    Look into project_name.runs/synth_1/runme.log
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    [SOLVED]Closed: Re: vivado post route simulation problem

    A synthesis log is always generated by Vivado. Have you checked that thoroughly? That's a fiest check.
    Can you see the signal d[0:7] there?
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    Closed: Re: RS232 Spartan 3E testing

    Assuming your design is functioning properly, a common problem is baud rate matching.
    Make sure the rate at VHDL UART and your PC console application is the same.
  21. Closed: Re: Module 'xyz' does not have a timeunit/timeprecision specification in ...

    1. Get a repo, SVN, Git -- best solution!
    2. Get a filelist or .f file (tracking of files possible but not their contents). More details here -...
  22. Closed: Re: Module 'xyz' does not have a timeunit/timeprecision specification in ...

    I am seeing what you have written and it includes none of your project files. So I find it difficult to answer your question.
    What if you remove the file in question from Modelsim project, add it...
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    Closed: Re: Import chipscopes data to matlab

    Sorry, my bad......didn't read #1 thoroughly.
  24. [SOLVED]Closed: Re: Creating verilog define for filename based on input file path, string concatenati

    What happens if you use the absolute path inside the RTL?
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    Closed: Re: Import chipscopes data to matlab

    I don't use Matlab!
    So I jst gave the basic idea of using scripts. Now if it can be done in Matlab, good for the OP.
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