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Type: Posts; User: fouwad

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  1. Closed: Re: What is wrong with this Mux code using indexing?

    The error in Xilinx 10.1 is "TO_INTEGER can not have such operands in this case" when i write



    process(inp, sel)
    begin
    sig_out <= inp(TO_INTEGER(unsigned(sel)));
    end process;
  2. Closed: Re: What is wrong with this Mux code using indexing?

    internet says best way to do is "b <= to_integer(unsigned(a));" but whenever i use this statement, Xilinx gives me errors, I am using Xilinx 10.1 ISE
  3. Replies
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    1,460

    Closed: Re: How to burn hex file into AT89C51 ?

    use external burner for your microcontroller, you will find many external universal microcontrolller programmers on which you will put your controlller and it will burn for you
  4. Replies
    6
    Views
    2,798

    Closed: Re: Board to board connection

    149526

    149527
  5. [SOLVED]Closed: Re: Looking for a datasheet on dc-to-dc-converter IC MP3300Dn

    you usually dont find datasheets for those Chinese modules or even dev boards. best to show its picture to old electronics guys and they may be able you

    - - - Updated - - -

    or cut it open to...
  6. Closed: Re: Unable to find AC power supply module fortektronix dpo3054 Oscilloscope

    absolutely nothing, the tek part numbers have changed, the country representative of tektronix have no idea what to do, its out of stock from farnell and other suppliers, I cant even find the power...
  7. Closed: What is wrong with this Mux code using indexing

    ----------------------------------------------------------------------------------
    -- Company:
    -- Engineer:
    --
    -- Create Date: 14:48:40 09/27/2018
    -- Design Name:
    -- Module Name: ...
  8. Replies
    11
    Views
    909

    Closed: Re: Verilog : synthesis Error

    You have assigned out once here
    "always @(posedge clk)
    begin

    out <= out + 1;
    end"

    and second time here

    "
  9. Replies
    11
    Views
    909

    Closed: Re: Verilog : synthesis Error

    You have assigned out to outputs of two module's outputs, that is why you are getting error. assign it to single module and it will work.
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    2,802

    Closed: Re: Ethernet Switch can be used as Ethernet hub?

    HUB and Switch both serve the same purpose but HUB is a dumb terminal while Switch is an intelligent device. Hub broadcasts while Switch reads the IPs and route the packets efficiently
  11. Replies
    25
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    9,928

    [SOLVED]Closed: Re: AMD or Intel for engineering PC?

    AMD processors are quite prone to dusty and hot temperature. And from where you belong, it is better to use Intel Processor in your PC. Increase your RAM to 16GB and use hard disk with good data...
  12. Replies
    3
    Views
    514

    [SOLVED]Closed: Re: What does this assignment mean?

    if you under stand HDLs then b[2:1] is compared to c whose output will be either 1 or 0. Logical AND the result with d.var and then store the result into A.
  13. Closed: Re: Voltage sampling in high power high voltage buck converter

    It is always better to be on the safe side, add an isolation amplifier or any liner opto or galvanic isolator. This will not only reduce the current into your ADC but also save your design from any...
  14. Closed: Unable to find AC power supply module fortektronix dpo3054 Oscilloscope

    I have tektronix DPO3054 oscilloscope and it stopped working. The display went off. I downloaded the service manual and found out that if +12V, +6V does not show on connector, replace the AC power...
  15. Replies
    10
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    2,460

    [SOLVED]Closed: Re: Initializing Xilinx BRAM with image pixels

    use .coe file to initialize your memory ROM at startup
  16. Closed: Re: Xilinx ISE - readmemh system task taking too much time

    You may use .ini file to initialize the memory, I am not sure if the readmemb is synthesizable or not
  17. Replies
    3
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    1,930

    Closed: FPGA interface with 100Mbps Ethernet

    Hello guys,
    I wish to interface FPGA with 100Mbps ethernet, I have found numerous ICs, some support MAC and PHY while some support only PHY. I need some jump start on this, can anyone guide me how...
  18. Replies
    13
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    2,583

    Closed: Re: Help tracking down very long synthesis time

    What PC or Laptop are you using?
  19. Closed: Multisim simulation file for LM2575 switching regulator

    Hello guys, i need a .cir file for LM2575 regulator. can someone please provide a link for it. TI website has .DSN files , if there is a way to convert DSN to cir file. please let me know thanks.
  20. Replies
    11
    Views
    1,041

    [SOLVED]Closed: Re: FPGA interface with LQ300+ Dot matrix Printer

    Got it thanks, plus its working with a loopback cable without any control signals. Last thing, how can i change the default configuration of the printer as there are no DIP switches in this model. by...
  21. Replies
    4
    Views
    978

    Closed: Re: Clock frequency after place and route

    there is a difference between a theory and practical. He needs to test it
  22. Replies
    11
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    1,041

    [SOLVED]Closed: Re: FPGA interface with LQ300+ Dot matrix Printer

    Thanks guys for your responses, I interfaced the printer serially using RS232 and converting the 25Db to 9pin DB interface. The combination that i used for conversion is given in the image below....
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    10
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    1,290

    Closed: Re: fpga for dsp in vhdl language

    Utilize that IP core, bring it into the project, go to design utilities and see the HDL design for it. the internet codes do not work most often.
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    1,630

    Closed: Re: Help in verilog for MIPS design

    It happened with me too, reset all the signals and memories and give reset at the start of teshbench. if registers are not initialized with any value and assigned a value in the middle of the logic,...
  25. Replies
    4
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    978

    Closed: Re: Clock frequency after place and route

    you may test your design by running post route simulation , if the signals are generated ok and are green, the signals may be ok, if red then your clock is too fast for the system.
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