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  1. Closed: Re: How do I reduce power at synthesis stage? I cant use UPF, Clock gating or retimin

    Can you use high Vt Cells if timing allows? This will reduce static power though.
  2. [SOLVED]Closed: Re: $urandom_range is generating same values

    Thank you for detailed explanation. This makes sense to me. I was able to use -seed random in Cadence xrun to get desired behavior.

    Thanks!
  3. [SOLVED]Closed: $urandom_range is generating same values

    I am writing a test bench where I am randomizing few inputs using $urandom_range(max,min). However, every time I am running my test, it is returning same value. I would like to understand why I am...
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    Closed: Re: priority on two asynch triggered events

    With if else you are adding a priority code. It does not matter if it is reset or any other signal, with if else you are coding priority.
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    Closed: Re: [Verilog] Asynchronous Reset

    I will suggest you to take a look at D flip flop internal structure and see how asyn reset factors into output. Coming back to your question, if switching delay of reset from 0 -> 1 is extremely slow...
  6. Closed: Cadence SimVision waveform dump for parameterized multibit signals

    Hey,

    I just switched to Cadence SimVision from Verdi for simulations. For parameterized multibit signals in waveform dumps, I am seeing hex values instead of parameter names. I looked into...
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    Closed: Re: Static Timing Analysis

    Generally if you have a setup violation on a given path, you do not have hold violation on same path. You can probably have hold violation on some other fanin cone of endpoint which you can fix by...
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    Closed: Re: Clock domain crossing problem

    Of course you cannot add synchronizer for multi bit data and this is due to reason #1 (no guarantee for delay). You will need DMUX synchronizer or FIFO for multi bit data.
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    Closed: Re: Clock domain crossing problem

    This is interview question which test possible issues with synchronizations. Nothing more than that :)
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    Closed: Re: Clock domain crossing problem

    1. You cannot simply synchronize data from clock domain A and B to clock domain C and then perform the combinational operation. This will result in classic problem of re-convergence. With...
  11. Closed: Re: latches in timing (do latches get timed as destination or as combo logic)

    Synthesis tool should look at both paths as previously stated. There are few processor based companies that uses latch based designs with internal timing tools to gain from timing borrowing and...
  12. Closed: Re: How to fix setup timing violations for a design with high speed clock?

    1. Can you use higher metal layers for routing to reduce interconnect delay?
    2. Pipeline.
    3. Upsize cells.
    4. Add buffers to reduces interconnect delay.
    5. Add low Vt cells which are faster but...
  13. Closed: Re: is the race condition normally observed in RC timing analysis?

    As others mentioned question is not making much sense. It is be a good idea to read more about static timing analysis. Feel free to post relevant question if you encounter after that.
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    [SOLVED]Closed: Re: Fixing setup violations in RTL

    Fixing timing violations in RTL generally means changing your design. As a designer you can come up with a different way that architecturally/functionally will yield same output but uses less...
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    Closed: Re: CMOS inverter output ?

    1) Remember that VDD is required to charge or discharge the output load capacitance. Also remember that X in silicon is an unknown value. Keeping these 2 things in mind, when Vdd is off, then output...
  16. Closed: Re: why does power no longer scale with technology?

    With scaling down of channel length or improvement in technology node to 10 nm or 7 nm (for example), there are new areas that started becoming predominant. These are probably new factors (aka static...
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    [SOLVED]Closed: Re: What does this assignment mean?

    Just to add, d is a struct/union whose element var is accesses which is 1 bit signal as well.
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    Closed: Re: Design Compiler Command Needed

    get_clocks.
  19. Closed: Re: How does lowering the voltage makes transitor more leaky?

    Read about channel effect with scaling from any good book. There are lot of other effects that happen as channel length is reduced.
  20. Closed: Re: how to solve a setup hold conflicting path

    Borrowing is basically splitting your flop in positive level latch and negative level latch. Read about time borrowing and you will figure it out.
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    Closed: Re: Serdes IP integration to ASIC

    Yes you can provide the IP as Soft IP and Hard IP.


    In case of Soft IP you can do so. However, Hard IP is like a black box. You cannot change anything inside RTL for Hard IPs.
    For hard IP, you...
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    Closed: Re: how to include a module in another module?

    What I suggested should work. I have seem code similar to what I said in my company few times. Let me know if you need more clarifications.
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    Closed: Re: Test Coverage loss scan chains

    Please through more information here. Question is not clear.
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    Closed: Re: how to include a module in another module?

    If you want to include a verilog code, then remove module and endmodule from comparator.v. That way your include will be plain Verilog code as part of test_module. It will work fine in synthesis and...
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    Closed: Re: Serdes IP integration to ASIC

    In general for any IP to be integrated in SOC (for instance) require power domain requirements (possibly UPF), clock domain requirements, input/output details and any common standard interface for...
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