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Type: Posts; User: Dominik Przyborowski

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  1. Closed: Re: Can't find "portAdaptor" in Virtuoso

    Look for it in the spectre installation directory
  2. Closed: Re: wide band operational amplifer

    It's ordinary Miller OTA working in class A-AB.
    it is wideband because is not narrowband (it is not a joke).
    Don't pay too much attention to names.

    More precisely, this guy is WB because can...
  3. Closed: Re: Ideal switched capacitor circuit - voltage spikes

    The buety of numerical simulations...
    You can try VerilogA, apply some delay in vcvs, try to play with ahdlib blocks or simply use value() function to plot the waveform composed from points...
  4. Closed: Re: Ideal switched capacitor circuit - voltage spikes

    If I understood properly, gain in vcvs is important.
    Try to use svcvs element instead of vcvs.
    Svcvs is vcvs with Laplace transfer function, so you can implement 1st order opamp using it...
  5. Closed: Re: Ideal switched capacitor circuit - voltage spikes

    I'm not sure whether is possible to remove discontinuity using relay element.
    If you need ideal system for behavioral modeling, why not write VerilogA module for mdac?
  6. Closed: Re: TSMC 0.18um Breakdown voltage

    There are various breakdown mechanism and we can distinguish:
    1. Hard breakdown (permanent damage)
    2. Soft breakdown
    Also, transistor is complicated device so, various types of breakdown can...
  7. Closed: Re: TSMC 0.18um Breakdown voltage

    Read process documentation. There is an answer for your question.

    And be mercy ul for us.
    You even didn't mentioned what kind of transistors you are using.
    Also, what kind of breakdown you have...
  8. Closed: Re: Ideal switched capacitor circuit - voltage spikes

    I am too lazy to calculate.
    What has bigger impact - gain of vcvs or rise time of clocks?
    If gain (gain of vcvs is 1M, cap divider is 1m product is 1k) decrease gain
    If rise/fall time of clocks,...
  9. Closed: Re: DC operating output voltages of the Fully differential amplifier is not equal

    I'm a bit uncertain whether bsim3 models contains any WPE or LOD parameters. It means, that if dc level differs between schematic and extracted netlist, something is wrong with extraction.
  10. Closed: Re: Monte Carlo simulation with TSMC 0.13u

    Everything is in process documentation.
    You should use devices with postfix "_mac" . You can switch you devices manually or by script (if exist in your PDK setup)
  11. Closed: Re: Netlist is different between schematic and layout

    Such conclusion is too strong and is wrong in general. The devil is in details, as usual.
    As long as distributed admittances around the structure can be considered as negligible, it might work...
  12. Closed: Re: Netlist is different between schematic and layout

    I am merciful today ;-)

    In the schematic netlist you have only mosfets - model of channel below the gate oxide.
    In the layout, your p-channel mosfets are putted in the n-wells, which are an...
  13. Closed: Re: Netlist is different between schematic and layout

    Diode. Do you know such device?
  14. Closed: Re: RHP poles always appear in my designed amplifier

    I have tried some small gain multistage and they are working on simulations.

    RHP is a sign that somewhere you have positive feedback. It might be result of odd number of stage and tricky...
  15. Closed: Re: CMFB biasing current in fully differential Opamp with adaptive current source

    It's all true. CMFB does not matter in many points, but can kill performance of IP3 or response on the kickback noise from SAR ADC loading opamp. Also, if output swing is rail to rail, then loussy...
  16. Closed: Re: Trans-impedance Amplifier using OTA.

    The issue is lack of understanding the testbench.
    First of all use ac amplitude set to 1 not 1m. In closed loop simulation, you should achieve transimpedance - relation between output amplitude vs...
  17. Replies
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    Closed: Re: MOSFETs connected in series

    Look on attached figure. I hope it should dispel your doubts.
    157248
  18. Closed: Re: VMware Linux CentOS Cadence memory RAM limitation

    Is the system 64bit? What uname -a says?
  19. Closed: Re: Including geometric variation of transistors using Montecarlo simulation in Cade

    Simply, read this friendly manual. In this case, your process documentation. For your process is nice and short document about Mismatch and how it is modeled as well.
  20. [SOLVED]Closed: Re: ADEXL simulation problem in cadence

    The simplest solution - use recommended system, in this case it is RHEL5 or 6.

    If in $HOME/.vnc-cds/eda:80.log is stated only such 4 lines, it simply means that your system gcc version is not...
  21. [SOLVED]Closed: Re: ADEXL simulation problem in cadence

    I am considering myself as a lazy person, but ok.

    The issue is related to used by ADE XL mechanism of running job process by calling vnc protocol. The vnc server starts to checking whether system...
  22. [SOLVED]Closed: Re: ADEXL simulation problem in cadence

    The issue is well known and the solution you can find on this forum, too.
    Hint: look on the point 3 in message you're get (1921).
  23. [SOLVED]Closed: Re: ADEXL simulation problem in cadence

    What is stated in job.log?
    What is your Linux distribution?
  24. Closed: Re: Resistor mismatch hand calculation and simulation

    There is something called "error propagation law". This should be teacher at every school during laboratory measurement, so you should be able to find a lot of materials on it.
  25. Closed: Re: SFDR of DAC obtained from its INL and DNL

    The only thing you can get is an upper limit of SFDR, by projection of generated sinusoidal waveform through DAC transfer function. However, it can be still far away from true SFDR of your DAC
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