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    Closed: Re: UPF for low power design in DC/ICC2

    you don't say what you are trying to achieve, I don't understand what you expect as feedback...
  2. [SOLVED]Closed: Re: 128 x 32 single port RAM VHDL code problem

    correct. disregard my message... wrong forum.
  3. [SOLVED]Closed: Re: 128 x 32 single port RAM VHDL code problem

    no idea. can you at least describe what you are expecting versus what you are getting?

    ps: tell your instructor memories are not synthesisable, this is a very poor exercise.
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    Closed: Re: Latency and skew of clock tree

    It's a tradeoff. the more you push, the faster the circuit runs, but more power it burns. you have to reason with the design spec (maybe you are obliged to hit that sweet 2GHz frequency) and with...
  5. Closed: Re: How to evaluate the energy of an arithmetic operation

    I agree that having different testbenches for each use case is the simplest way to go.
  6. [SOLVED]Closed: Re: How to automate the maximum frequency estimation

    the binary search wouldn't necessarily reduce the time. in typical binary search problems, you are interested in exploring both branches of the solution space. here is different because both branches...
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    Closed: Re: Latency and skew of clock tree

    It's hard to think that clock skew/latency can be reused from previous project unless they are very similar in size, same node, same relative number of clock tree leafs.

    You may want to play with...
  8. Closed: Re: Max Overdrive Supply Voltage in SoC 5nmFinFet

    I would think 1.2 is really pushing it. But one thing worth mentioning is that just because you supply 1.2V externally, it doesn't mean the transistors actually get 1.2V. Maybe the degradation is...
  9. [SOLVED]Closed: Re: How to automate the maximum frequency estimation

    I have seen people do two approaches:
    - start from impossible constraint (1ps clock period) and relax as you go.
    - start from relaxed constraint (99999999ps clock period) and tighten as you go.
    ...
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    Closed: Re: Latency and skew of clock tree

    how did you decide the target latency and skew? start from there
  11. [SOLVED]Closed: Re: Low power optimization problem in competitive vendor economics ?

    this crap again about nop instruction? get a clue.
  12. [SOLVED]Closed: Re: How to check un-clocked flops and how to trace the source point for the problem ?

    You have made such a humongous mistake that it should not need any explanation. TRACE THE DAMN LOGIC. FIND WHERE THE CLOCK IS MISSING. How hard is this? Have you actually tried? What is stopping you?
  13. [SOLVED]Closed: Re: How to check un-clocked flops and how to trace the source point for the problem ?

    check your design, check your SDC. trivial debugging. missing a clock is huge.
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    Closed: Re: VCD File as a input to Cadence Virtuoso

    The funny part is that they probably had a testbench of sorts written in some known language. From there, it got converted to VCD and you "converted" it back to a simulation trace. Sigh.
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    Closed: Re: VCD File as a input to Cadence Virtuoso

    VCD is the output of a simulation, not the input. I have no clue what you are trying to achieve.
  16. Closed: Re: How to display ASCII state when simulating one-hot encoding FSM ?

    you can create mnemonics in the simulation environment, regardless of how you coded the states. it's handy.
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    Closed: Re: Capacitacne tables in UMC 130nm

    I would not recommend trying SE, that is already too old. maybe there is some tool that can generate a QRC file out of a captable? maybe UMC can help you with that
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    Closed: Re: Capacitacne tables in UMC 130nm

    try using encounter instead of innovus. 130nm is legacy technology these days.
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    Closed: Re: Finding an IP Power Analysis Tool

    any synthesis tool will do this for you. try genus or dc.
  20. Closed: Re: Unbuffered cells and how does it affect timing constraints

    It looks like there are two indexes for input transition, and one index for load.

    I would guess this is somehow an approach to account for the S-shaped curve instead of a perfect transition on...
  21. Closed: Re: PrimeTime : How to manually assign the content of the nets

    I am guessing here, but I guess the issue is related to using the right tool for the right job. PrimeTime does STA, in which the worst case has to be assumed and that means it has to consider all...
  22. Closed: Re: Unbuffered cells and how does it affect timing constraints

    for timing, the 2D tables are related to the input transition and to the output load. I am not sure I understand what the third dimension is. Are you sure it is called output load?
  23. Closed: Re: The difference between '|' operator and keyword 'or'

    see this: http://www.asic-world.com/verilog/operators.html

    click on logical operators and on bitwise operators. the difference should be clear.
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    Closed: Re: Boundary Cell in Core Chip

    both assertions are incorrect. endcap cells are about well termination and timing consistency, regardless of cell location (near or far from an edge). welltaps are about bulk/well connections, not...
  25. Closed: Re: Preferred shell for scripting, csh or bash?

    there is a lot of legacy stuff in environment scripts and tool installation scripts. so we keep using the same stuff over and over.
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