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  1. Closed: Re: SystemVerilog Behavioral Simulation in Cadence Virtuoso/AMS/Incisive/Spectre

    I know what .sv is.

    I am talking about analog / mixed signal simulation.
  2. Closed: SystemVerilog Behavioral Simulation in Cadence Virtuoso/AMS/Incisive/Spectre

    Hello,

    I want to do behavioral simulations using SystemVerilog as opposed to using Verilog-A and Verilog-AMS for Mixed Signal Designs in Cadence Virtuoso/AMS/Incisive/Spectre.

    How can I use...
  3. Closed: TSMC65nm CRN65LP PDK Calibre and PEX Issues

    Hello,

    I am having some issues with TSMC65nm CRN65LP PDK Calibre and PEX Issues - mainly setitng up PEX for Calibre and TSMC65nm CRN65LP PDK for HCell/Xcell and avoiding the double counting of RF...
  4. Closed: Re: Physical Verification with TSMC65nm CRN65LP PDK

    no one uses tsmc65nm PDK here ?
  5. Closed: Re: How to measure the C parasitic (internal capacitance) of an inverter using Spectr

    This value has to be derived from simulation.

    I understand properly - you just dont know the answer.

    Also, Cadence Spectre is a simulator. Just letting you know that.
  6. Closed: Re: How to measure the C parasitic (internal capacitance) of an inverter using Spectr

    You are right - this is an inverter driving another inverter.

    I am looking for Cpar - which is the capacitance of the driving inverters internal capacitances without any load of another inverter. ...
  7. Closed: Re: How to measure the C parasitic (internal capacitance) of an inverter using Spectr

    Please see attached picture for inverter.

    I am looking to measure Cpar = Cw in that picture. Cpar being the parasitic capacitance.

    - - - Updated - - -

    Cgate is Cint in that picture.
  8. Closed: How to measure the C parasitic (internal capacitance) of an inverter using Spectre ?

    I want to measure the Reff of an inverter.

    I know how to measure the Cgate of the inverter.

    But how do I get the Cpar of the inverter (that is-the internal capacitance).

    Then use these two...
  9. Closed: Re: Need documets related to extraction of Inductance using Cadence Assura

    Just use EM simulation. You would need an interface between Cadence (if you are using that) and Keysight ADS - it is called GoldenGate for Keysight Momentum (an EM Simulator). It can simulate...
  10. Replies
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    Closed: Re: NCSU FreePDK 15nm for Analog Design

    There is always Cadence's General Purpose PDK's, for using the flow of their software and tools and yes, they have a FINFET GPDK.
  11. Closed: Re: CMOS FINFET Layout Tutorials/Explanations

    i just want to learn how to do it. also not all PDKs offer "any help" or tutorials - especially on how to do layout.

    i am going to answer my own question here: i will use Microwind to learn how...
  12. Closed: CMOS FINFET Layout Tutorials/Explanations

    What are the best resources (papers, books etc) to learn FINFET layout ?

    Can anyone share any ?
  13. Replies
    2
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    344

    Closed: NCSU FreePDK 15nm for Analog Design

    Hello,

    Has anyone used this NCSU kit for Analog Design ?

    Or is it mainly for digital design (standard cell flow).

    Thank you.
  14. Replies
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    Closed: Re: Decoupling Capacitance in IC Layo

    To this point, I have a few questions.

    When doing over 10 GHz amplifier designs, I usually tend to EM simulate the supply lines to determine the amount of RLC in the DC path and then use that to...
  15. Replies
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    672

    Closed: Re: Decoupling Capacitance in IC Layo

    So you just add as much decoupling as you can depending on your layout at the IC level ?

    Just any amount ?

    - - - Updated - - -



    --
  16. Replies
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    672

    Closed: Supply Decoupling Capacitance in IC Layouts

    If doing an analog or RF layout, how much decoupling capacitance do you use in the layout for supply decoupling and, for RF layout, for supply feed line decoupling ?

    How do you calculate these...
  17. Closed: Re: Spice .INC file into Cadence Spectre/DFII

    What if I have no model file chain and this is all I am using ?
  18. Closed: Spice .INC file into Cadence Spectre/DFII

    Hello,

    I have a spice model for a process in .INC format.

    How can I use this file to do simulation using Cadence Spectre ?

    I would assume .include model.inc - but where do I add this ?
    ...
  19. Replies
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    Closed: Length of Path in Cadence Virtuoso/DFII

    Hello,

    I have a non straight, meandered line/path in Cadence Virtuoso/DFII.

    Is there a command to measure the length of this path ?

    Thank you.
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    Closed: Incisive Intallation using Installscape

    Hello,

    Want to install Incisive add on to Cadence DFII using Installscape on Centos 6.

    Do I tell Installscape where DFII installation is already and then install Incisive ?

    Does Incisive...
  21. Closed: Re: Converting verilog code into a symbol during AMS simulation

    https://community.cadence.com/cadence_technology_forums/f/custom-ic-design/35255/easy-way-to-connect-a-input-bus-pins-in-schematic
  22. Closed: Re: Physical Verification with TSMC65nm CRN65LP PDK

    Now I was told for my version of Calibre 2017, I have to do the following for this PDK:


    In LVS rule file add:


    LAYOUT CELL LIST pcells “rf component here*” “rf component here*”
    LAYOUT...
  23. Closed: Physical Verification with TSMC65nm CRN65LP PDK

    Hello,

    This posting is similar to an earlier posting:

    https://www.edaboard.com/showthread.php?280164-Physical-verification-with-TSMC-CRN65LP-v1-7a-PDK

    I do not have the hcells file.

    How...
  24. Replies
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    360

    Closed: DNL/INL Measurement in Cadence for DAC

    DNL

    https://milindsweb.amved.com/Calculating_DNL_in_Cadence.html

    INL

    https://milindsweb.amved.com/Calculating_INL_in_Cadence.html
  25. Closed: Re: INL/DNL Measurement from Cadence Spectre/Virtuoso Output

    Hello,

    Your answer is nonsense.

    In the future, please answer the question being asked.

    That's all.

    Thank you.
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