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Type: Posts; User: Cesar0182

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  1. Closed: How I can make use of the resources of only certain regions of the device in Vivado?

    Greetings ... tell you that a few days ago I translated a single verilog file to vhdl to add it to my vhdl project in Vivado 2017.3 which has the function of controlling the transmission and...
  2. [SOLVED]Closed: Re: Error: Subprogram does not have a body when creating vhdl packa

    I just fixed it, I wasn't getting it very much. This is my new code.


    BIBLIOTECA ieee;
    USE ieee.std_logic_1164.all;
    USE ieee.std_logic_unsigned.all;
    USE ieee.std_logic_misc.all;
    USE...
  3. [SOLVED]Closed: Re: Error: Subprogram does not have a body when creating vhdl packa

    Thanks for answering ads-ee ... I'm not sure what you mean by "indexed" name is not a type.
    I have made some changes based on the data sheets...
  4. [SOLVED]Closed: Error: Subprogram does not have a body when creating vhdl package.

    Greetings ... comment that I am new creating vhdl packages and a couple of days ago I am trying to create one, but I am having the following error shown in the image.

    156119

    Can someone please...
  5. Closed: Re: What is the vhdl equivalent of "initial begin" to initialize a ROM.

    Thanks for answering FvM, tell you that S1_CLKOUT0_FRAC_EN or S1_CLKOUT0 if they are parameters and S1_CLKOUT0_FRAC_A and others are signals that I had to create since I could not make a direct...
  6. Closed: What is the vhdl equivalent of "initial begin" to initialize a ROM.

    Greetings ... tell you that a couple of days ago I am trying to translate a verilog file to vhdl and I found the next block that initializes a ROM.



    // Make sure the memory is implemented as...
  7. Closed: Re: Problem calling a function from my vhdl project in Vivado.

    Thanks for the help. Is there a rule for this type of verilog syntax for vhdl? because the examples are not clear to me. Tell you that I did the translation based on the following link...
  8. Closed: Problem calling a function from my vhdl project in Vivado.

    Greetings ... comment that a couple of days ago I am trying to translate an .h file to vhdl, this in order to be able to use the functions in my vhdl project. The truth is that I am new doing...
  9. Closed: Re: Help to make use of an .h file in my vhdl code

    Ok, thank you very much for the help
  10. Closed: Re: Help to make use of an .h file in my vhdl code

    Okay, if there is no other way, I will start translating my .h file to vhdl.
    Another question I have is the use of "initial begin" in verilog. Is there any equivalent in vhdl for this?
  11. Closed: Re: Help to make use of an .h file in my vhdl code

    When I include it directly, it gives me the following error shown in the attached image.

    155732
  12. Closed: Re: Help to make use of an .h file in my vhdl code

    Do you suggest that you translate my .h file to vhdl so that it can be included in my code as a library?
  13. Closed: Re: Help to make use of an .h file in my vhdl code

    Could you please explain how I include this .h file to my code through a package or library?
  14. Closed: Help to make use of an .h file in my vhdl code

    Comment that I am trying to translate a verilog file to vhdl, but so far I am having trouble using an .h file in my vhdl code.
    Someone who can help me with this problem please, leave the verilog...
  15. Closed: Problem when implementing Vivado 2018.3 project with python script in Cygwin

    Greetings ... tell you that a couple of days ago I have a project in Vivado 2017.3, which correctly implemented it from the cygwin terminal with a python script using Vivado 2017.3.
    Now the problem...
  16. Closed: Re: How to increase the memory capacity of the IP core fifo_generator in Vivado 2018

    I told you that I made the change of the variable Almost_Full_Depth = 1000, but I still do not have any change .... reviewing the waveforms of a particular fifo (u_client (0)), where apparently is...
  17. Closed: Re: How to increase the memory capacity of the IP core fifo_generator in Vivado 2018

    thanks for the help Ads-ee ... you suggest that you increase the value of Almost_Full_Depth ?. As for the .xci file, do I need to modify some value?
  18. Closed: Re: How to increase the memory capacity of the IP core fifo_generator in Vivado 2018

    I already commented that I made the change only of Write Depth from a value of 512 to 1024 (as shown in the attached image), but this has not worked for me, I'm still trying to see the problem in the...
  19. Closed: Re: How to increase the memory capacity of the IP core fifo_generator in Vivado 2018

    I commented that the way I'm checking is through the simulation, where you are using 26 fifos with a 52-bit write and read bus, as far as I understand the fifos (fifo_generator v13.2) of my system...
  20. Closed: How to increase the memory capacity of the IP core fifo_generator in Vivado 2018.3?

    Greetings ... tell them that I am new using the IP cores in Vivado, and I would like to know if it is possible to increase the memory capacity of the fifo_generator IP core v13.2? And how is the...
  21. [SOLVED]Closed: Re: Problem with the synthesizer when I update Aurora 64B v9.1 to v11.2 in Vivado 201

    thanks Ads-ee, your help is always useful ... what I do not understand is how can I update an IP gradually?
  22. [SOLVED]Closed: Problem with the synthesizer when I update Aurora 64B v9.1 to v11.2 in Vivado 2018.3

    Greetings ... tell them that I am new using IP cores, and a couple of days ago they passed me a project (vhdl sources and IPs) where the IPs were made in Vivado 2013.4. I have managed to synthesize,...
  23. Closed: Re: Problem to simulate project when updating IP made in Vivado 2013.4

    thanks for all the help Add-ee, I attach the vhdl code of the module where these fifos are located.



    library IEEE;
    use IEEE.std_logic_1164.all;
    use IEEE.numeric_std.all;
    use...
  24. Closed: Re: Problem to simulate project when updating IP made in Vivado 2013.4

    thanks for your answers ... following the recommendation of Add-ee only update the core and run the simulation, but the problem persists and is the one shown in the following images.

    Passed...
  25. Closed: Problem to simulate project when updating IP made in Vivado 2013.4

    greetings ... firstly, I said that I am new by personalizing an IP core and a couple of days ago they gave me a project which uses IPs that were made in Vivado 2013.4. I am currently using Vivado...
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