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Post map simulation in Xilinx ISE 10.1

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tariq786

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how to simulation ise xilinx

Hi,
I am doing the whole fpga design flow on AES (Advanced Encryption Standard Core).The behavioral simulation in modelsim works fine but when i run the post translate or post map simulation in modelsim, i get 0 at the output that is my output is always 0.

Why is this the case?

Any ideas? Am i correctly simulating? or do i need to do more to simulate?
Please let me know.

Thanks

Kind Regards
 

xilinx post simulation

Do you see any setup or hold time violation popping up on your modelsim console...
 

xilinx ise 10 simulation howto

no i dont see.
 

xilinx ise mapper -k

Hi,
check if sdf warnings and errors are not disabled in the simulation. if they are disabled, you will not see any errors.
 

xilinx ise post simulation

how to check that?
 

xilinxise 10.1

there is a switch in command vsim. I think -sdfwarn.
In GUI also, in start simulation window, you can find check boxes which will be something like "diasable sdf errors to warnings" and like.
 

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