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Signal Integraty Schematic

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Mahen K

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I am new to board design and trying to learn Signal Integrity Analysis. Attached the the actual schematic as shown in Fig 3.1 where as Fig 3.2 and Fig 3.3 are equivalent Signal Integrity Schematics. All three figures are from the first example in the HyperLynx manual. Can anybody explain how does the Fig 3.1 translate into equivalent SI Schematic as shown in 3.2 and 3.3? i.e which net in Fig 1. translate into which transmission line in Fig 3.2 and Fig 3.3?

Thanks in Advance
Mahen K
 

Hi,

signal integrity (or SI) refers to PCB interconnection design. Therefore each piece of trace needs to be indicated in the simulation model.
Each piece of trace is a TRANSMISSION LINE (like 50 ohm RF stuff you know) characterized by its characteristic impedance (be careful it is not necessary 50 ohm) and its lenght, that, in this case, Hyperlinx models as its delay.

If you see Fig. 3.2, you have your driver IC, then a first Transmission Line (from now on TL) going to the T-split, and then other two TL going to the 2 74xxxx inputs which are the receivers.

Following the same scheme you should find out the equivalent schematic of Fig. 3.3.
Good Luck
 

Rossano, Thanks but my questionwas how is Fig 3.2 equivalant to Fig 3.1.

-Mahen
 

Mahen,

442ps microstripe is the net between the 7402 output and the T split. 73.8ps microstripe is the 74244 input bonding, 351ps microstripe is the trace between the two 74244 inputs, and the last 73.8ps mictrostripe is the chip bonding.
If you don't take into account the chip bonding, you get Fig.3.3
 

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