Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

decimation factor of a three stage cic filter

Status
Not open for further replies.

lgeorge123

Full Member level 2
Joined
Jun 13, 2004
Messages
130
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,296
Location
Hong Kong
Activity points
1,403
In a three stage cic filter and the decimation factor is 32 , does it means that overall decimation is 32*32*32 ( 32768 )or just 32 only?

- - - Updated - - -

I search the google found it only 32. For dso in fixed 100MHz sampling clock to adc , can I achieve lower the sampling rate like selecting 1ms , 5ms etc time base by passing adc 8 bit output data to cic filter in adjusting different decimation factor??
 
Last edited:

What do you exactly mean with "three stage CIC"? The decimation factor is the ratio of input to output sampling rate, independend of the CIC order.
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top