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Verilog: displaying Real number during simulation

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sctneh

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i'm currently doing a simulation debug involving calculations. The real numbers i'm interested to observe involve some maths regarding $realtime. I believe something's wrong in the behavioral model of the PLL when it's calculating the period of the refclk/fbclk etc...

Unfortunately, the data stored as "real" cannot be pulled out as sim waveforms. Is there a workaround? Is it possible to store the real numbers into "reg", and then display the waveform? Pls advice...many thanks.
 

Why can't you probe real signals in your waveform viewer? Which simulator are you using?
 

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