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Timing ARC for Asynchronous Signal

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Varun124

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Hi All,
I have some doubt regarding timing arc. What is timing arcs. Is there any hardcore rule that if any port is asynchronous signal then it should have timing arc??
 

Varun124 said:
Hi All,
I have some doubt regarding timing arc. What is timing arcs. Is there any hardcore rule that if any port is asynchronous signal then it should have timing arc??
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unclear. are you talking about timing arcs within a standard cell or within a design?
 

Yes within stand cells
 

the rule is simple: any input that causes a change to an output is considered during std cell characterization. the tools that are farther up in the implementation chain need to know the delay and power consumption associated with a toggle on the input.
 

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