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Instantiation In a Loop in Verilog

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reza.ghanaatian

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Hi,

I want to instantiate a module 16 time and it is so boring.
Is there a way that I can use a "for loop" and only one istantiation?
I used these syntax and ModelSim doed not accept it.
I should say that I need my code to be synthesizable also.
 

Seems like you lacking a good Verilog text book or tutorial. Read about the generate loop statement.
 

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