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vivado synthesis multithreading

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vahidsh

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Hi dear engineers,
I want to khnow about vivado features:
1- In vivado is it possible to synthesis the design with for example 8 CPUs (multithreading)?
2- When i script the " set_param general.maxThreads 8" in TCL console and then synthesis the design, synthesing the design are multithread or other level also ( like place and route level ...) has been multithread?
Thnks alot.
 

Hi dear engineers,
I want to khnow about vivado features:
1- In vivado is it possible to synthesis the design with for example 8 CPUs (multithreading)?
2- When i script the " set_param general.maxThreads 8" in TCL console and then synthesis the design, synthesing the design are multithread or other level also ( like place and route level ...) has been multithread?
Thnks alot.

At first I thought was a silly question about designing a multiple CPU design...

The multi-threading support for the tools is purely a tools software issue. If it's supported it will be used and will only use the number of computer CPUs that the program was written to use. You can't just arbitrarily set it to some value like 8 when the tools don't even support 8 threads, as of 2015.1 (I haven't installed 2015.4) it uses only 4 threads max for any step of the compilation and some are 2 or 1.
 

My PC CPU is core-i7 and it has 8 cpu core but synthesisng and other level of my design take too many time to run. And when i monitor the performance of cpus i found that just 4 of them are busy and others are free.
I've been read your answer. Did you meant that changing the maximum number of CPUs is not achiveable?
 

The software "Vivado" has support for multithreading with 4 CPU threads and some of the steps only have support for 2 CPU threads. So no you can't magically make Vivado use 8 CPUs.

To make it run faster, use partitioning and lock partitions that won't change, check that you didn't over constrain the design or have too many constraints that overlap. Check if you pipelined the design correctly (if it has to work really hard to meet a timing constraint due to too much logic between registers that will slow synthesis dramatically). Or buy a faster gaming computer, put in one of those liquid cooling systems and overclock it.

Seems like you should read UG949 Ultrafast Design Methodology for pointers.
 

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