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zero cycle path setup violation

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atulpatil6370

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Hi folks,

I have seen few zero cycle ( set_multicycle_path 0) setup paths in design. Can you explain why there is a need of having 0 cycle setup path? what is a advantage of the same? How do we check hold violations for these kind of paths?

These paths are violating setup time. How can fix this issue in cadence encounter
 

These are several points below:
1. 0 cycle setup would be a problem in design itself. Please review with your designer. What is the reason for the path to be existed.
2. If it is right from designer, please do clock latency adjustment, which extend delay of capturing clock and shorten launch clock delays. Of course, you need to make sure below:
- No side effects for others paths related to these 2 FFs.
- Hold timing is good.
 

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