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One clock cycle delay for the input data

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riz1679

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Hi all, I am new to digital design. shown in the figure there is an 'addr' signal which is generated by some state machine. I want to sample the input data 'data_rec_in' with one clock cycle delay. Below is the code for the block.



Code:
[ATTACH=CONFIG]149499._xfImport[/ATTACH]
 

Hi,

usually just a (additional) DFF is used to delay by one clock cycle.

Klaus
 

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