Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Shift register will parallel load

Status
Not open for further replies.

sandy2811

Junior Member level 3
Joined
Jul 20, 2012
Messages
25
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,450
How can design shift register with parallel load...................
 

1. Decide about the intended function like asynchronous or synchronous load
2. Write a behavioral description from the scratch
or
3. Copy the gate level circuit of a respective logic IC, e.g. 74165, 74166.
 

You already have code for an up/down counter with preload, modify it for shifting...

Code Verilog - [expand]
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
module preload_counter(q,
                       clk,
                       rst,
                       en,
                       load,
                       preload,
                       upd
                       );
                       
input clk,rst,load,upd,en;
input [2:0] preload;
integer c;
output [2:0] q;
reg [2:0] q;
 
always @(posedge clk)
begin
   if (rst)     
     q <= 3'b000;
 
    else if (load)
        q <= preload;
       else if(upd)
       // else
      begin
         q <= q + 1;
         if( q == 3'b111)
           begin
           c = 1'b1;
           $display("Counter is full count = %b and c = %d",q,c);
           end
         end
       else 
         begin
         q <= q - 1;
         if( q == 3'b000)
           begin
           c = 1'b0;
           $display("Counter is empty count = %b and c = %d",q,c);
           end
       end
end
         
 
endmodule



Just change the lines for q <= q + 1 and q <= q - 1 to perform a shift left/right instead of an increment/decrement.

FYI as I never code with blocking assignments inside a edge triggered always block, I can't be absolutely sure, but I think c might end up as a latch since it isn't defined in all branches of the if statement and will therefore have to be held at whatever state it was last, i.e. it becomes a latch.
 

How can design shift register with parallel load...................

I have posted here a code for PISO(parallel in serial out) few years back. Its in VHDL though, but in both behavioral and structural methods.
 
Last edited by a moderator:

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top