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Problem in using Verilog-a in hspice

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akbarza

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hi
i wanted to run a simple verilog-a in hspice 2013 that are as below:

Content of resistor.va as:

Code:
// Simple resistor

`include "disciplines.vams"

module resistor(p,n);
parameter R=1.0 from (0:inf);
electrical p,n;
analog I(p,n) <+ V(p,n)/R;
endmodule


Content of resistor.sp file as:

Code:
*Title: Simple Verilog-A Resistor
.hdl resistor.va
.options post=1
X1 1 2 resistor r=1 
*r1 1 2 1
r2 2 0 1
VS 1 0 1 
.dc VS 0 10 1
.probe v(2)
.end
when i run resistor.sp in hspice , some file is produced but .lis file is empty( 0kb) and nothing is written on it and nothing occurred.
i search this site and search net. in some thread, the problem is related to licence, but i don't know how to check it or correct it.
for clarity, i write the name of files created after runing hspice:
  • resistor.sto
  • resistor.valog
  • resistor.lis
  • resistor.pvadir(folder)
please guide me
 
Last edited by a moderator:

There should be a log file, I'd think, and there you would find
clues about what it didn't like (and if you're lucky, why). Or
some barf-wad in the console / control window, depending
on what your version looks like.

From what I've seen, there is usually an intermediate step
in using veriloga models, taking them to a C compiled model
that SPICEs tend to support directly (code models). I see
no discussion of this in your problem description, whether
it succeeds, fails or never even is tried. I have seen that
some SPICEs manage this, and some expect you to go and
do the compile and link in the object model yourself.Check
the HSPICE docs about that.
 

Content of resistor.valog as :

Code:
 --------------------------------------------------------
|                                                        |
|          Synopsys Unified Verilog-A (pVA v3.0)         |
|                                                        |
|              Machine Name: DESKTOP-FNK1C3V             |
| Copyright (c) 2013 Synopsys Inc., All Rights Reserved. |
|                                                        |
 --------------------------------------------------------

libepva built by hspmgr synmake_pva_build  on Wed Jul 24 10:18:53 CST 2013
HSP_HOME:   C:\synopsys\Hspice_H-2013.03-SP2
HSP_ARCH:   win64
HSP_GCC :   C:\synopsys\Hspice_H-2013.03-SP2\GNU\win64\bin\gcc
HSP_GCC_VER:   3.4.5
Working-Dir: C:\Users\safir rayaneh\Desktop\veriloga-hspice
Args:        -p hsp -t spi -f resistor.pvadir/pvaHDL.lis -o resistor.pvadir 

### optimize mode ###
Args: pva -p hsp -t spi -f resistor.pvadir/pvaHDL.lis -o resistor.pvadir

Begin of pVA compiling on Fri Dec 07 11:31:02 2018

Parsing './resistor.va'
Parsing include file 'C:/synopsys/Hspice_H-2013.03-SP2/include/disciplines.vams'

End of pVA compiling on Fri Dec 07 11:31:02 2018


End of build pVA DB on Fri Dec 07 11:31:02 2018

*pvaI* Module (resistor): 2 unexpanded port, 0 init, 1 behav, 1 contrib, 11/0 expr(s)
*pvaI*        No DIS, 0 afCount, 0 MT
*pvaI*        1 const-G and 0 const-C, No switchBranch, 0 bypassOpt
*pvaI*        generated 0 flow node(s) during compilation.

End of pVA genC on Fri Dec 07 11:31:05 2018

*pvaI* #### Total 99 line-size(s), 11/0 expr(s), 1 contr(s), 0 init(s), 1 behav(s), 2 port(s)

Generating resistor.pvadir\pvaRTL_win64.dll



pVA concluded on Fri Dec 07 11:31:29 2018
 

in resistor.lis file, it is found:

Init: read install configuration file: C:\synopsys\Hspice_H-2013.03-SP2\meta.cfg
**error** call to epvaHDLinit failed.
**error** Failed to read Verilog-A file, see <design>.valog file for details.
**error** (resistor.sp:2) difficulty in reading input
but file resistor.valog did not be open with notpad++ and other apps.
 
Last edited by a moderator:

The compilation appears to have finished with no complaints,
but seems the "real deal" cannot be read. Possibly you need
to tell HSPICE where to look for this

"resistor.pvadir\pvaRTL_win64.dlldll" file

or that it needs to look, in the first place? I dunno.
 

hi dick_freebird
can uoy explain more? suppose you are right, what do i do?
 

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