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[SOLVED] Instantiating module with inout

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ranayehya

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Hello!
I am new in verilog and I begin working on I2C protocol hardware implementation
The master code works well
Capture.PNG
but when I combine all files together the master code does not work as it was
Capture.PNG
"sda_reg" is the problem and I do not know what I did wrong
the top code
Code: 
module top;
wire clock,reset,start;
wire [7:0]addr;
wire [7:0]data;

wire [7:0] out;


wire scl_w ,sda_w ;
master m1(.clk(clock),.start(start),.reset(reset),.addr(addr),.data(data),.scl(scl_w),.sda(sda_w));
slave s1(.scl(scl_w),.sda(sda_w),.data(out));

endmodule
And "sda" is inout
This is the piece of code related to "sda" (from master code)
Code: 
assign sda = enable? sda_reg : sda;
 

Code Verilog - [expand]
1

assign sda = enable? sda_reg : sda;

Makes no sense. You want to tristate SDA when disabled instead of forming a latch.
 

Hello, FvM!
In the first image, "enable" signal was = 1. So sda = sda_reg and that works
In the second image, "enable" signal was = 1. sda should = sda_reg but this is not happening
When "enable" =0, the master will read from the slave (acknowledge bit)
I managed this piece in my code, but I can not see the result because of this don't care in my simulation
If you want the master code, please inform me and I will edit the post
Thanks!
 
Last edited:

The code for driving the tristate at the output should be in this form:

assign sda = (sda_low) ? 1'b0 : 1'bz;

One point of confusion I suspect: when sda is being 'driven' to z it will still 'read' 1 or 0 for the purpose of the rest of your code depending on the pin's actual state.
 

Thanks to you all for commenting. It works when I write it in that way.

assign sda = enable? sda_reg : 1'bz;
 

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