Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

What's the difference between stacked and cascode configurations?

Status
Not open for further replies.

circuitking

Full Member level 5
Joined
Jan 8, 2018
Messages
291
Helped
1
Reputation
2
Reaction score
1
Trophy points
18
Activity points
2,503
Hi This question already being answered here but I want some clarifications.
https://www.edaboard.com/showthread...de-configurations&highlight=stacked+amplifier


Millimeter-Wave Power Amplifiers by Jaco du Preez, Saurabh Sinha
stack_amplifier.JPG

In the figure, if I don't connect the capacitors (Cn) at the gate terminals then it becomes cascode and if I connect capacitors then it is stacked configurations. is that it?

"The bottom device is configured in a common source mode, while the remainder
of the transistors are operated without grounding any particular terminal in a
common-gate-like setup. "

1.If I imagine the small signal model, the gate teminals will definately be grounded because capacitor is short for AC and VGNs are connected to ground. I don't understand what they mean by that.

"The configuration shown in Fig differs from a cascode amplifier where the common-gate transistor is grounded at the center
frequency. In a stacked design, the gate terminal of the common-gate-like device is
connected to some finite impedance and the drain voltages are added in phase in an
ideal situation"

2.They say some finite impedance, does it mean it can be anything not just capacitance (like resistance, inductance or complex).

3.In the FIgure, it is written Ropt, why does it need to be just resistance, it can be anything right? (I was thinking that I would get that Ropt from loadpull and ignore the imaginary part )
 
Last edited:

I would call this figure a double-cascode, one FET is actively
driven and the others have static gate bias.

If you look at RF CMOS switches, those are stacked and all
of the gates are co-driven "on" or "off".

Don't overthink the "difference", there may be none except
idiom.
 

In the figure, if I don't connect the capacitors (Cn) at the gate terminals then it becomes cascode and if I connect capacitors then it is stacked configurations. is that it?
No. In the previous thread, it's just the other way round.

Quite clearly, usual cascode configuration has the second (or possibly third) stage in CG, gate grounded. Apparently the author refers to stacked as a configuration where the second gate is also actively driven. Like dick_freebird, I'm not sure if this is commonly agreed terminology.
 

No. In the previous thread, it's just the other way round.

Quite clearly, usual cascode configuration has the second (or possibly third) stage in CG, gate grounded.
What do you mean by gate grounded exactly?
Apparently the author refers to stacked as a configuration where the second gate is also actively driven.
Do you mean we can give input to the second gate also? But it doesn't show like that in the figure.

Can I also say cascode configuration is also a stacked configuration with N=2? Then I will not have any confusion.
 

In the figure, if I don't connect the capacitors (Cn) at the gate terminals then it becomes cascode and if I connect capacitors then it is stacked configurations. is that it?

This is cascode nevertheless. The capacitor does not serve any purpose here.

See the following figure.

cascode_vs_stacked.png

In cascode, C_CAS >> C_GS and therefore the gate is a virtual ground (Rb in combination with C_CAS forms a low pass filter) The look in impedance is 1/gm

In stacked, the C_ST is of the same order as C_GS and the look in impedance can be written as (approximately) (1/gm)*(1+ C_GS/C_ST). Because the input impedance is no longer low, the swing in the source will be larger. This reduces the drain to source swing of the cascode transistor.
By the way, the price you pay for going for a stacked configuration is that the gain is not as high as cascode.

- - - Updated - - -

3.In the FIgure, it is written Ropt, why does it need to be just resistance, it can be anything right? (I was thinking that I would get that Ropt from loadpull and ignore the imaginary part )

Yes it can be anything. Typically people place a matching network between a common source and common gate device.
 

Nice Explanation.
In stacked, the C_ST is of the same order as C_GS and the look in impedance can be written as (approximately) (1/gm)*(1+ C_GS/C_ST). Because the input impedance is no longer low, the swing in the source will be larger. This reduces the drain to source
I never connected C_CAS in any of my cascode topologies till now. In Conclusion for stack configuration, I should make sure C_ST is of the same order as C_GS.
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top