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dc offset problem - need suggestion concerning a circuit

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dc offset

it is a two stage programmable amplifier, the core amp is an ota, inorder to cancel the dc offset, a feedback loop is adopted. however,
traditional structre(in Razavi's book) can not be used here, because the loop circuit is very sensitive to load.

can anyone give me some suggestion, thanks very much![/img]

 

dc offset problem

I wander whether you drawed the schematic completely.
I designed a fourth order filter with DC offset cancellation.the feedback block acts as a LPF to extract the dc signal of the output. And the BW of the LPF is very low.so the value of R and C is very large.
For the main signal path,the load is only R. when you design the amplifier, This should not be a problem because the R is very large.
 

Re: dc offset problem

Hi,
I wonder why your loop circuit sensitive to load, it seems Sever loop DC-offset cancelling circuit will be okay in your case.
 

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