Ironlord
Member level 3
Hello.
I want to implement the SPI protocol in VHDL over an FPGA.
My question here is quite simple, I want an option in order to decide which frequency to use. For example, if I have a fast device as an screen an a slow device as a sensor I need to communicate them with different frequencies.
As my FPGA works @50MHz I thought it would be a great idea to make a clock divider, so I would work with 50, 25, 10, 5, 2 and 1Mhz.
How is the best way to implement them? I could define some values and count them, but I also can have 6 clocks at the same time.
This last option would be something like this:
So I would have 6 process. I guess this is not the best option, but I'm not sure if generating clocks from counters is such a good idea.
I want to implement the SPI protocol in VHDL over an FPGA.
My question here is quite simple, I want an option in order to decide which frequency to use. For example, if I have a fast device as an screen an a slow device as a sensor I need to communicate them with different frequencies.
As my FPGA works @50MHz I thought it would be a great idea to make a clock divider, so I would work with 50, 25, 10, 5, 2 and 1Mhz.
How is the best way to implement them? I could define some values and count them, but I also can have 6 clocks at the same time.
This last option would be something like this:
Code:
Process(CLK50) is
If(rising_edge(CLK50))then
CLK25<=NOT(CLK25)
End if;
End Process;
Process(CLK25) is
If(rising_edge(CLK25))then
CLK10<=NOT(CLK10)
End if;
End Process;
So I would have 6 process. I guess this is not the best option, but I'm not sure if generating clocks from counters is such a good idea.