[SOLVED] How do I read a test bench input from a txt file?

Code VHDL - [expand]
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--read process
 process is
    file txt_file   : text;
    variable line_v : line;
    variable slv_v  : std_logic_vector(11 downto 0);
    variable good_v : boolean;
  begin
   
    file_open(txt_file, "Input.txt", read_mode);
    readline(txt_file, line_v);
    report "line_v: " & line_v.all;
    read(line_v, slv_v, good_v);
    file_close(txt_file);
    y<=slv_v;
    wait;
  end process;

Code VHDL - [expand]
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process
           variable v_ILINE     : line;
           variable v_OLINE     : line;
           variable v_ADD_TERM1 : std_logic_vector(c_WIDTH-1 downto 0);
           variable v_ADD_TERM2 : std_logic_vector(c_WIDTH-1 downto 0);
           variable v_SPACE     : character;
            
         begin
        
           file_open(file_VECTORS, "Input.txt",  read_mode);
        
           while not endfile(file_VECTORS) loop
             readline(file_VECTORS, v_ILINE);
             read(v_ILINE, v_ADD_TERM1);
             read(v_ILINE, v_SPACE);           -- read in the space character
             read(v_ILINE, v_ADD_TERM2);
        
             -- Pass the variable to a signal to allow the ripple-carry to use it
             y <= v_ADD_TERM1;
             
              
          
           end loop;
        
           file_close(file_VECTORS);
            
           wait;
         end process

Code VHDL - [expand]
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while not endfile(file_VECTORS) loop
  readline(file_VECTORS, v_ILINE);
  read(v_ILINE, v_ADD_TERM1);
  read(v_ILINE, v_SPACE);           -- read in the space character
  read(v_ILINE, v_ADD_TERM2);
        
  -- Pass the variable to a signal to allow the ripple-carry to use it
  y <= v_ADD_TERM1;
  wait until rising_edge(clk_out1);          
end loop;