mahmood.n
Member level 5
I am using Active-HDL to write VHDL codes. I am able to write ans simulate one file codes but when it comes to multiple source files and components, the simulation doesn't work! It seems that there is a problem finding components in other source files. Please see the attached picture.
As you can see in the left pane, the test bench is selected as the top level. Any idea for that? the code is pretty simple and should work!
As you can see in the left pane, the test bench is selected as the top level. Any idea for that? the code is pretty simple and should work!