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how to simulate SNDR and SFDR of ADC with HSPICE

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mohsen941

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hi my friends
i have been designed 10-bit 50M sample/s Successive Approximation ADC in CMOS 0.18um technology
i have been used HSPICE for simulation, now i want to test my DAC's SFDR, SNDR and ENOB spec in Hspice.
i really have not any information about this. is there any good reference for it?
i have no time for doing it, please help!!!!!!!!!!!!!!
so many thanks in advance
 

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