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Error loading systemC design unit on ModelSim SE 10.0e

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ceet

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Dear all,

I'm new on this forum and I'm glad to join your community.

I face a problem when I try to simulate a systemC program with ModelSim. Here the message error:

Code:
# vsim work.sc_main 
# ** Note: (vsim-3812) Design is being optimized...
# ** Error: (vopt-7) Failed to open debug database file "/work/_sc//moduleinfo.sc.link" in read mode.
# ** Error: (vopt-3675) Could not find shared library "/work/_sc//systemc.so for SystemC module 'sc_main'.
# ** Warning: (vopt-7) Failed to open SystemC shared library file "/work/_sc//systemc.so" in read mode.
# No such file or directory. (errno = ENOENT)
# ** Error: Failed to find design unit work.sc_main.
# Optimization failed
# Error loading design

Here the macro .do I use to compile and launch simulation:
Code:
# Create library
vlib work

#Compile systemC source
sccom -64 test.cpp

# Link
sccom -64 -link

#Load design
vsim -novopt sc_main

# Launch simulation
run -all

And here my simple source code:
Code:
#include "systemc.h"

SC_MODULE(MyModule)
{
  sc_signal<sc_logic> mySignal;

  void myThread();

  SC_CTOR(MyModule)
  {
    SC_THREAD(myThread);
  }
};

void MyModule::myThread()
{
  mySignal.write(SC_LOGIC_0);
  wait(100, SC_NS);
  mySignal.write(SC_LOGIC_1);
}

int sc_main(int argc, char* argv[])
{
  // ***************
  // * Elaboration *
  // ***************
  MyModule *my_module = new MyModule("myModule");

  // **************
  // * Simulation *
  // **************
  sc_start();
 
  // *******************
  // * Post-processing *
  // *******************
  delete my_module;
  
  return 0;
}

I have no problem loading and simulate VHDL design. Could it be a license issue ?
 

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