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Synthesizing design modules with different constraints.

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My question is based on edf file (after sythesis)

say my design is divided in to 12 different bolcks, now i am sythesizing top module, calling all modules in that top module. keeping synthesis constraint same for all and getting edf file format after synthesis.

i want to know can i synthesis different module with different synthesis constraint and finally merge all edf, module wise in top level entity. if yes how to do that??

Thanks.
 

Yes Surely you can do that . In mentor tool for RTL precison tool you can go block by block and do synthesis and find the edif file. People often do that as there might be the case when each module might hve different contraints for the design.
vipul
 

Don't know if this works for you or not:

current_design block_A
... contraint for A ...
current_design block_B
... contraint for B ...
current_design top
... other constraints ...
compile -inc
 

thanks to all for responding

but now question is how to integrate those sub modules in top level????? Also it is required to get edf for top level module??
 

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