FPGA implementation of feature extraction module from images

Hi

i am putting togather a feature extraction module from facial images on FPGA.

I have half of my algorithm ready and i can find the face in an image,then the eyes and all features from the eye. I have done all of this on Matlab and i am interested in putting this module on fpga. Most of my code uses general mathematical calculations like addition and subtraction etc.

But I have never worked with FPGA boards before and would like to know How does one access the on board RAM and flash memory to store picture and data generated while executing the algorithm. i need to manage certain output of the algorithm, store them and access them again.


I am using a Altera DE2 cycloneII FPGA board.

folowing are the specification of the board

Altera Cyclone® II 2C35 FPGA device
• Altera Serial Configuration device - EPCS16
• USB Blaster (on board) for programming and user API control; both JTAG and Active Serial
(AS) programming modes are supported
• 512-Kbyte SRAM
• 8-Mbyte SDRAM
• 4-Mbyte Flash memory (1 Mbyte on some boards)

If some one can help me in getting started on this project.

I will be thankful

Varun

PS: i dont want to use any conversion tool to generate a VHDL module from Matlab

Re: FPGA implementation of feature extraction module from im

come on guys....tell me something ...if it can be done or not....i am requesting u again..just show me some direction..thats all i ask

Re: FPGA implementation of feature extraction module from im

It can be done, but it is not so easy. You probably should check about NIOS II and SOPC Builder. I would recommend starting by watching all the videos in the Altera site about embedded programming.

Check from here: http://www.altera.com/education/training/curriculum/soc/trn-soc.html

Re: FPGA implementation of feature extraction module from im

hey

thanx alot for guiding me through

appreciate ur help

i am going through the video as my work permits..

if it is simple algorithm and if possible send me your code, I will try to make verilog code.