Vhdl - numeric_std.signed error (number conversion error)

Hi, I am working on a school final project. Within a process statement, I am trying to do logical shifts on two signed inputs (x1 and x2) and then add the values of x1 and x2 and then store it into a signed signal called sDFF1 (which represents D-Flip-Flop 1). After I get out of the clocked process I want to store the signed sDFF1 value into a D-Flip Flop which I call DFF1. I try instantiating my D-Flip-Flop component (DFF1) but get the number type errors below from the compiler. I need to work with signed numbers. Below is the ERRORs, my code for the D-Flip-Flop, and my code for the design. Does anyone know how to fix these errors?

Thanks for everyone's help! :razz:

ERRORS:
# ** Error: D:/Profiles/w30239/My Documents/Miscallaneous/ECE 584/Project/Example Code Rader/RaderExample.vhd(24): Signal "sDFF1" is type ieee.NUMERIC_STD.SIGNED; expecting type ieee.std_logic_1164.STD_LOGIC.
# ** Error: D:/Profiles/w30239/My Documents/Miscallaneous/ECE 584/Project/Example Code Rader/RaderExample.vhd(24): Signal "C" is type ieee.NUMERIC_STD.SIGNED; expecting type ieee.std_logic_1164.STD_LOGIC.

CODE FOR D-Flip-Flop:
library ieee;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;

entity DFF is
port(D : IN signed (7 downto 0);
Clk : in std_logic;
Q : OUT signed (7 downto 0));
end DFF;

architecture behavior of DFF is
begin

process (Clk) -- Change of Clk .
begin
if (Clk'event and Clk='1') then -- Clk event and positive edge. (Change Clk=?0? for negative edge)
Q <= D;
end if;
end process;

end behavior;

CODE FOR DESIGN (which calls the D-Flip-Flop Component):
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;

entity RaderExample is
Port (x1 : IN signed (7 downto 0);
x2 : IN signed (7 downto 0);
Clk : in std_logic;
C : OUT signed (7 downto 0));
end RaderExample;

architecture Behavioral of RaderExample is

component DFF
port(D : in std_logic;
Clk : in std_logic;
Q : out std_logic);
end component;

signal sDFF1 : signed (7 downto 0);

begin

DFF1 : DFF port map (sDFF1,Clk,C);

CLK_PROC : process (Clk)
begin
if rising_edge(clk) then
sDFF1 <= (x1 sll 1) + (x2 sll 2);
end if;
end process CLK_PROC;

end Behavioral;

component DFF
port(D : in std_logic;
Clk : in std_logic;
Q : out std_logic);
end component;


DFF1 : DFF port map (sDFF1,Clk,C);

Here you map it to signed (7 downto 0);

similarly C : OUT signed (7 downto 0)); first
but component part Q declared as Q : out std_logic);


Actual and formal parameters must be same type

---------- Post added at 23:17 ---------- Previous post was at 23:09 ----------


why do you need 7bit for a D Flip Flop ?

Thanks Blooz. That fixed my issue. I need an 8 bit D-Flip Flop because I need to store a new 8 bit number upon each clock cycle.

jerryt said:

Thanks Blooz. That fixed my issue. I need an 8 bit D-Flip Flop because I need to store a new 8 bit number upon each clock cycle.

Click to expand...

Your component "DFF" is not needed. You will get the same result like this:

Thanks std_match but in the design project I am working on there are are delay elements (registers) in which I need to use D-flip flops for. I want to make sure I mandate that the VHDL compliler/synthesizer uses the HW as pertained to the design. Please see the diagram of the block needed to be designed.

View attachment Block.bmp

Thanks std_match but in the design project I am working on there are are delay elements (registers) in which I need to use D-flip flops for. I want to make sure I mandate that the VHDL compliler/synthesizer uses the HW as pertained to the design. Please see the diagram of the block needed to be designed.

It will do exactly that. Std_match's code is exactly the same as the code using the DFF. It is all behavioural code. So there is nothing special about your DFF component.

That's some good information. Thanks everyone for your help!