HDL simulators inner workings

Hi folks, I have a question about HDL simulators like Synopsys VCS or Cadence NCVerilog or Mentor Graphics ModelSim

Do you know how HDL simulators work inside?

For example,
I am always curious how would HDL simulator simulate the following sum of product (and-or-invert gate)

//////////////////////////////////////////Beginning of Verilog code ////////////////////////////////////////////////
module and_or_invert_gate(output z,
input a,b,c,d
)

wire y;

assign y = (a & b) | (c&d);
assign z = !y;

endmodule
/////////////////////////////////////////////// End of Verilog Code ////////////////////////////////////////////////////////////////////

I mean what does the simulator do when it sees an & symbol in the Verilog code? How does it simulate it? What algorithm is used?

Similarly how does it model concurrency as both assignment states are executing in parallel?

What are the pre-processing steps of HDL simulation?

Most importantly, how does HDL simulator know it has simulated correctly.

If you can share some documentation, that will help me pick up HDL simulation quickly, that would be very much appreciated.


Thanks a lot.

The Verilog Document IEEE 1364 Has a section dedicated to simulation reference model
and scheduling semantics

Verilog has a discrete event execution model .A design consists of connected threads of execution or processes.
Processes include primitives, modules, initial and always procedural blocks, continuous assignments etc .


VHDL standard 1076 also has a detailed chapter on Elaboration and execution

User sees everything happening once but all the processes in background runs one by one. This done with the help of Scheduling (computing). Designing a simulator is very complex task involving hundreds of engineers and result of research of many years.

Preceding the actual simulation are two major steps (for VHDL): Ref: A VHDL primer by Bhasker
1. Elaboration phase: In this phase, the hierarchy of the entity is expanded and linked, components are bound to entities in a library and the top-level entity is built as a network of behavioral models that is ready to be simulated. Also, storage is allocated for all data objects (signals, variables, and constants) declared in the design units. Initial values are also assigned to these objects.
2. Initialization phase: The effective values for all explicitly declared signals are computed, implicit signals (discussed in later chapters) are assigned values, processes are executed once until they suspend, and simulation time is reset to 0 ns.
Simulation commences by advancing time to that of the next event. Values that are scheduled to be assigned to signals at this time are assigned. Each process that has a signal in its sensitivity list whose value just changed, is executed until it suspends. Simulation stops when a user-specified time limit is reached, or when an assertion violation occurs, depending on the implementation of the VHDL system or when the maximum time as defined by the language is reached.

Simulation algorithms:

Some interesting topics

Cycle based Simulation

h**p://codeidol.com/hardware/hardware-design/Coding-for-Verification/Cycle-Based-Simulation/


Digital logic simulation: event-driven, cycle-based, and home-brewed
h**p://edn.com/archives/1996/070496/14df4.htm

Cycle based Simulation
h**p://cs.haifa.ac.il/courses/Verification_Seminar/sim_verification/Cycle%20Based%20Simulation.htm

yadavvlsi & Blooz, my friends. So nice of you

Warm regards