Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

why different clock period in different corners

Status
Not open for further replies.
J

jaya sree

Member level 3
Joined
Nov 9, 2009
Messages
55
Helped
2
Reputation
4
Reaction score
2
Trophy points
1,288
Location
india
Activity points
1,791
Hai everyone ,

In my project i have different time periods in different corners. (1642 ps in in SSp072v AND 1000 IN TTp85v ). why the clock time periods are different.They should be same at all scenarios and corners right ? please answer this doubt.

thanks
 

Re: why different clcok period in different corners

it is due to the clock skew..random skew..the parts far from the clock source suffer greater delay than the parts nearer to the source.. it areses due to the track capacitance..
u can reduce it by keeping the track size almost same.. try using spline method for designing your board..even H method is the best..or try to keep the clock source in the center ...however the track length should be the same
 
Re: why different clcok period in different corners

jaya sree said:
Hai everyone ,

In my project i have different time periods in different corners. (1642 ps in in SSp072v AND 1000 IN TTp85v ). why the clock time periods are different.They should be same at all scenarios and corners right ? please answer this doubt.

thanks
Click to expand...

Jaya , I agree with your view on clock edge should be same in a corner. But when speaking about scenario, SDC's are mode specific and may be in your case, the SDC for your particular mode has different clock definition. Can you check the same.
 

Re: why different clcok period in different corners

Can u elobrate the question?.....question is not clear....is your are refering to board design or FPGA internals...
 

Re: why different clcok period in different corners

yes the clock periods are different in sdc's . there are different sdcs for different corners.but why sdc must vary with different corners ? cell delays and net delays vary for different corners. this i undertand . but should clock period and sdc must be different in different corners. This question is related to asic physical design flow
 

Re: why different clcok period in different corners

is it quite normal, no?
In our design we target a running frequency for the TT corner and another one for the slow corner, and one other for the best corner, because we know "we are" a bit aggresive at slow corner if we keep the TT frequency. By this, if all corners are loaded in PnR tool, it could fix the setup for all corners.
 
Re: why different clcok period in different corners

jaya sree said:
yes the clock periods are different in sdc's . there are different sdcs for different corners.but why sdc must vary with different corners ? cell delays and net delays vary for different corners. this i undertand . but should clock period and sdc must be different in different corners. This question is related to asic physical design flow
Click to expand...

Is it for different corners or different modes? I dont think it is for corner. For modes it is usual to have different clock definitions.
 
It is possible to have different clock rates for corners and modes. you can have TT corner with 1000ps but this may not be achievable in SS corner, some specify min and max rate for a given corner. modes are different from the corners and typically have different clock definitions
 
Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top