Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

How to write Verilog code for MBE multiplier

Status
Not open for further replies.
K

kuankuan

Newbie level 3
Joined
Nov 30, 2011
Messages
3
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,297
Hi,
I am new to verilog. I need to write verilog code for modified booth multiplier. How to write the code for padding 1 zero to LSB of a multiplier, let's say 4bits input?
Thanks.
Rgds,
KK
 

see how concatenation works in verilog

assign padded = {input,1'b0} //if padded is 5 bits
 
Thanks! I got it already.

another question:
If I have a 7bits multiplier, (let's say 0010110), how do I write verilog code to check for the bits in overlapping group of 3, such as (starting from lsb 110, then 101, then 001)? Assuming I do not know what is the actual multiplier number but I can fix it to 7 bits. I know I need to use LOOP but do not know exactly how to use the loop to check on the increasing iteration.
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top