Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

converting an array to a vector in VHDL

Status
Not open for further replies.
S

shaiko

Advanced Member level 5
Joined
Aug 20, 2011
Messages
2,644
Helped
303
Reputation
608
Reaction score
297
Trophy points
1,363
Activity points
18,302
Hi,

Suppose we have a VHDL array of 'n' elements and width of each element is 'k'.
How can we convert the array to a vector?

If we know the width and number of elements - we can use the concatenation operator:
-----------------------------------------------------------------------
type matrix is array (0 to 2) of std_logic_vector(7 downto 0);
signal concatenated_matrix: std_logic_vector(23 downto 0);

concatenated_matrix <= matrix(0) & matrix(1) & matrix(2);
-----------------------------------------------------------------------

But what if we want to write genericly ('k' and 'n' will be generics)
How can we code it?
 

May be write a function with for loop. Something like this.

for i in 0 to n loop
concatenated_matrix(k*i+k-1) <= matrix(i);
end loop;
 
  • Like
Reactions: shaiko

    S

    shaiko

    Points: 2
    Helpful Answer Positive Rating
you would need a function. (or wait until VHDL gets union types).

recall that my_array'range will return 0,1,2,...,N-1
recall that my_array(my_array'low)'range will return K-1,...,2,1,0
and the output is of size (my_array'length*my_array(my_array'low)'length-1 downto 0).

however, VHDL requires the function's input types be known. as a result, a single function cannot be used for any width/depth combo -- if you have 8b and 9b arrays, you'd a version of the function for each one, even through the code could otherwise be the same...
 
  • Like
Reactions: shaiko

    S

    shaiko

    Points: 2
    Helpful Answer Positive Rating
So...this type of code cannot be written genericly in VHDL?

---------- Post added at 13:42 ---------- Previous post was at 12:43 ----------

what about the following code (not in a function). given that "depth" and "width" are entity generics:

concatenating: for i in 0 to depth generate
concatenated_matrix((width - 1 + (i * width)) downto (i * width)) <= matrix(i);
end generate;

Will the above synthesize to a concatenated vector of all the array elements?
 

If I don't misunderstand the problem, it should work similar to vinipal's suggestion.

Code: 
for i in 0 to n loop
  concatenated_matrix(k*i+k-1 downto k*i) <= matrix(i);
end loop;

P.S.: I see, you found the solution yourself.
 
  • Like
Reactions: shaiko

    S

    shaiko

    Points: 2
    Helpful Answer Positive Rating
FvM, thanks for noting my mistake. I forgot the "downto" part..
 

Will the above synthesize to a concatenated vector of all the array elements?
Click to expand...

Yes it'll be fine, but it might be easier and neater to wrap it up in a function rather than a generate.

output <= concat_matrix( input );
 
  • Like
Reactions: shaiko

    S

    shaiko

    Points: 2
    Helpful Answer Positive Rating
Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top