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Increase in Area during CTS

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kumar_eee

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I'm interested in knowing parameters which will result in area increase during the CTS and Post-CTS Optimization.

I know a few parameters like skew, clock cell and drive selection & insertion dealy.. etc

Please add some more parameters if you know.

Thanks in advance.

Rgds,
Kumar
 

One more reason of area increasing is clock-gating replication during CTS. In some cases it will lead to better timing.
 

I think when fixing hold violations in CTS stage we may add delay buffers like that, then they can cause to increase the area
 

Hi Kumar,

I think that ,there are mainly three reasons to increase in area at CTS

1.At Cts Original clock will propagated (clock tree routed). Then skew factor come in to picture.To balance the skew more clock-buffers are added in clock path.
2.After clock balance i.e at post-cts stage, data paths will optimize to meet setup.
3.HFN(High fanout net) synthesis will happen i.e like cloning.

I dont think delay buffers are add at CTS stage As sharif mentioned . We concentrate on hold fix after route only.


Thanks,
Nari
 
HFN happens during placement i.e. Pre-CTS.

So, area increase would be mainly due to clock tree balancing (inserting buffers in clock tree and inserting clock gating cells) and hold time optimization .

Thanks,
Charan
 
Also 1 main point, congestion shoots up at CTS so cell spreading and buffering also is a factor to increased area.
 
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