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About spice simulating of extracted critical path ...

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Oveis.Gharan

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Dear all,
is there anyone who can tell me how can I extract spice netlist of critical path?
I have synthesized my moudules and i want to simulate the critical path with HSPICE but i do not know how could i extract spice netlist of critical path.

I am patiently awaiting for any guidance or suggestion.
Best Regards.
Oveis.
 

There is special command in PrimeTime for such task:

write_spice_deck [get_timing_path -from ... -to ...]

It will generate spice netlist, whic will consist of gates of the specified timing path, parasitics info fo the nets between these gates, input stimulus for spice simulation and spice measurement statements. These measurements are needed to compare timing between Ptime and spice.
 
Dear Oratio
Thanks a lot for your helpful guidance.

could i ask that what is the sequences should i follow that i could finaly use write_spice_deck option?

Thanks in advamce.
Oveis
 

In PrimeTime:

set link_library "your_lib.db" # specify your synopsys libraries
read_verilog ... # read your gate-level netlist
link
read_parasitics ... # read parasitics of interconnecting wires (derived from Place'n'Route tool, or manually create it, or skip this step)
read_sdc ... # read timing constraints (clock frequency etc)
report_timing ... # to see the critical pathes
write_spice_deck -header header.inc -sub_circuit_file library.spi -output output.sp [get_timing_path -from ... -to ...]
# header.inc should contains at least hspice statements like ".lib <model.lib>"
# library.spi should contains spice (transistor-level) netlist for each gates of your gate-level netlist
# output.sp is the final spice runset

Then, run Hspice
hspice output.sp

Then look in the *.mt0 file, that Hspice have generated. It will contains measurement results for all gates in your critical path, cell delay and transition time. The measurements named like delay_inv1/a_inv1/z, which means, that it is delay from pin inv1/a to pin inv1/z. You should find the same measurement in the PrimeTime timing report. If digits are equal (almost), it is good :) . If differs - how big difference - it is not good :(
 
Dear Pratie,

Thanks for your helpful comments.
I am verifying a fully combinational Block (ISCAS85 C432) and i have not set clock constraints yet and i only want to extract the critical path spice model. May the lack of .SDC file made the problem?

Thnks in advance.

---------- Post added at 13:21 ---------- Previous post was at 13:00 ----------

Dear Oratie
In PrimeTime:

set link_library "your_lib.db" # specify your synopsys libraries :(
I have linked the library :
set link_library NangateOpenCellLibrary_typical_conditional_ecsm.db

read_verilog ... # read your gate-level netlist
I did:
read_verilog C432_synthesize_no_exclusion.v
set_design_top Circuit432
the i linked them:
link
Code:
Linking design Circuit432...
Warning: Unable to resolve reference to 'TopLevel432b' in 'Circuit432'. (LNK-005)
Creating black box for Ckt432/TopLevel432b...
Information: Removing 6 unneeded designs..... (LNK-034)
Information: 134 (100.00%) library cells are unused in library NangateOpenCellLibrary.....
Information: total 134 library cells are unused.
Information: Issuing set_operating_conditions for setting analysis mode on_chip_variation. (PTE-037)
set_operating_conditions -analysis_type on_chip_variation  -library [get_libs {NangateOpenCellLibrary_typical_conditional_ecsm.db:NangateOpenCellLibrary}] 
Design 'Circuit432' was successfully linked.
1

read_parasitics ... # read parasitics of interconnecting wires (derived from Place'n'Route tool, or manually create it, or skip this step)
read_sdc ... # read timing constraints (clock frequency etc)
report_timing ... # to see the critical pathes
write_spice_deck -header header.inc -sub_circuit_file library.spi -output output.sp [get_timing_path -from ... -to ...]
# header.inc should contains at least hspice statements like ".lib <model.lib>"
# library.spi should contains spice (transistor-level) netlist for each gates of your gate-level netlist
# output.sp is the final spice runset
Then i could not do more becouse it could not link.
I did the linking this insted of "link" but it could not work again:
link_design -keep_sub_designs

but it responded these:
Code:
Linking design Circuit432...
Warning: Unable to resolve reference to 'TopLevel432b' in 'Circuit432'. (LNK-005)
Creating black box for Ckt432/TopLevel432b...
Information: 134 (100.00%) library cells are unused in library NangateOpenCellLibrary.....
Information: total 134 library cells are unused.
Information: Issuing set_operating_conditions for setting analysis mode on_chip_variation. (PTE-037)
set_operating_conditions -analysis_type on_chip_variation  -library [get_libs {NangateOpenCellLibrary_typical_conditional_ecsm.db:NangateOpenCellLibrary}] 
Design 'Circuit432' was successfully linked.
1
Indeed all the modules and sub modules are in the same read verilog file.
The sub modules are gate level.

What is the wrong thing ?

Best regards.
 

Try

set link_library "* NangateOpenCellLibrary_typical_conditional_ecsm.db" # added star in the link libraries

The "*" entry in the value of this variable indicates that the
link_design command should search all the designs loaded in pt_shell
while trying to resolve references. Designs are searched in the order
in which they were read.
 
I tried.
In this case the design was linked successfully :-o but the timing has not any items.
Code:
pt_shell> report_timing
****************************************
Report : timing
	-path_type full
	-delay_type max
	-max_paths 1
Design : Circuit432
Version: D-2009.12-SP1
Date   : Mon Nov  7 16:20:33 2011
****************************************

No constrained paths.

1
and when i want to write spice dec it responds :

Code:
pt_shell> write_spice_deck -header spice_header.txt -output c432_cp_spice.sp -logic_one_voltage 1.10 -logic_zero_voltage 0.0 -sub_circuit_file NangateOpenCellLibrary_pre.sp [get_timing_paths -from in1 -to out432 ]
Error: Nothing matched for collection (SEL-005)
1

The in1 and out432 are one of inputs and outputs respectively.
Then what should i do more?

Thanks for your concern dear Oratie.
 

Which timing constraints did you use for synthesis? set_max_delay or ...

The possible reasons of "No constrained paths" are: no any timing constraints; no timing violations (no negative slack).
The first reason may be solved by adding "set_max_delay <delay> -from in1 -to out432".
The second reason may be solved by "get_timing_path -slack ..." and by "set_app_var timing_report_unconstrained_paths true".
 
Dear Oratie
I have suceeded with your helps.
I am so appretiated for your helpful and wisely comments.

When i set (max_delay with "set_max_delay <delay> -from in1 -to out432") i could have a timing path in reports of report_timing command.

Then all things done O.K.
Best Regards and Thanks for all
Oveis Gharan
 

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