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[SOLVED] Gate Count v/s Instance count

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ajaytronic

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Hi All,

Can somebody explain, what is the difference between Gate count instance count?
I understand, Gate count is the number of equivalent NAND gate, but how it differs from instance count?

Does instance count calculates buffers also?

Thanks in advance
ajaytronic
 

The instance count is the actual number of standard cells in your design, and as you said, the gate count is the equivalent number of two-input nand gates that would occupy the standard cell area of your design.
 
The instance count is the actual number of standard cells in your design, and as you said, the gate count is the equivalent number of two-input nand gates that would occupy the standard cell area of your design.
Click to expand...

It is the total number of standard cell instance in the design. It includes all buffer/inverters. One buffer is also a instance.
 
Thanks yadavvlsi & eklikeroomys for reply.
Does it mean instance count always be more than Gate count ... as during optimization PnR tools add many buffer & inv to meet timing?

I also got to know that instance count need to take from the synthesis netlist (Without any optimization), please confirm if it is correct.

Thanks,
ajaytronic
 

Does it mean instance count always be more than Gate count ... as during optimization PnR tools add many buffer & inv to meet timing?
Click to expand...

Gate count will always be grater than instance count. A instance cab be a simple inverter or complex logic like MUX, AOI cell even a adder or multiplier. Yes, In most of the cases Instance count increases during PnR flow to meet timing requirements of the design. Initial instance count is taken from synthesized netlist (of course it is optimized what is the point in having instance count of unoptimized netlist.). Instance count varies as physical design flow goes from various steps.
 
Gate count will be higher. Instances are comprised of gates. It is easier to deal in instances than looking into a million gates :)
 
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