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verilog vs. vhdl..with keyword reg

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g.manju6@gmail.com

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i am stucked in vhdl can anybody tell how to write reg in vhdl..
my statement in verilog is [2:0]ex[3:0]..how to declare same in vhdl?:cry:
 

Declaring 2D, 3D or greater dimension arrays is a pain in VHDL.

In Verilog:

reg [2:0] ex [3:0];

In VHDL you cannot do this in one step. First you must declare a new type, an array of [3:0] elements. Only then can you declare the signal:

type ARRAY_EX is array of (natural range <>) of std_logic_vector (3 downto 0); -- type declaration, ARRAY_EX is the new type

signal ex : new_type (2 downto 0); -- signal declaration

Things get even more difficult when you need multi-dimensional arrays, because it requires a lot of new type declarations, one for each dimension.
 
Yes, one for declaring the new type and another to declare the signal itself.
 

Do you mean, how to assign a value to a signal?

To assign a value to a signal is similar to verilog, for example:

ex (1)(2) <= '1';
 

no suppose i created new type and signal..will both have same name or wt?
 

now i get it thanks for you answers...

---------- Post added at 15:15 ---------- Previous post was at 14:27 ----------

but am using more elements....assigning is problem.

will it work

data_out<=reg("addr");


where addr represents location
 

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