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Help for analog layout

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VarunKumar89

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Hi all,
I need your help in analog layout basics,
1) why the poly is made more longer than active area (vertically).
2) why the size of every via is kept constant.
Thanks in advance.

Regards,
Varun
 

1) In order to overcome possible mask misalignment, this rule secures total channel width coverage by the gate.
2) See here.
 
Thanks for your help.

Please tell me how the fabrication engineers decide the design rules. How they decide that Poly must extend this much value or nplus or pplus must extend this value from active etc.

Can mask misalignment not be controlled because the masks are created for whole wafer ( i guess) and wafers are around 8 inch to 12 inch size ( a macro size).
Also refer some data to study on this topics.

Thanks,
Varun
 

Each technological process has tolerances. Modern CMOS processes use 20 (vanilla) up to 40 (accurate analog with many options) masks, which have to be aligned to each other. Fab engineers measure misalignment, create statistics, and decide on design rules to avoid errors from misalignment.

Data on these topics are fab-confidential, sorry. Read books about semiconductor layout or mask fabrication!
 
I agree with erikl on via, bu also one issue with via etch is that larger vias or large arrays of vias/contacts are etching at different speed compared to single via. If vias have different sizes and you have large via next to a small one, the material would be etched out faster for the big one and smal via might not be even created. That was issue with older processes > 1um.
 
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