Purpose of Parasitic extraction from IC Package

Hi All,

I work in ic packaging layout. Recently, my client came out requesting for generating Parasitic(RLC Parameters) of Package pins i.e for solder balls. The package is wirebond package.

Now, my doubt is what they do with RLC value of package pins? Just to create IBIS model for the component or to perform certain functionality test? if so, what are all those test or just to know the inductance , capacitance effect in the package pin?

Thanks
prasguy

When you look into a chip, you have certain behavior. When you look into the device (that is the chip + package), the behavior may change.

If you have a chip input with 0.5 pF input capacitance and the package adds 0.2 pF, the device has 0.7 pF input capacitance. So when specifying a device, one has to include device parasitics.

When dealing with fast changing signals, the package (with bonding wires) can make the difference between a solution or no solution. So it is important to know the effect of the package on device performance.

Instead of supplying a model for each device, one can use a two-step approach.
A certain chip can be housed in various packages. A manufacturer may publish simulation models for the chip (without package), and (RLC) models for the package. To get a device in simulation, you just have to merge the chip model with the package model.

Once you have a good model for the package, you can reuse this for other chips.

Even for relatively slow signals the package can be of importance as bonding wires may generate heat and therefore may limit maximum current (though the chip itself may handle more current).


The other way around: If you have a device, and you want to characterize the chip, you need to know the behavior of the package.

Hi RfP,

Thanks for your reply. After providing that RLC of package, will you carry out any test/simulation? Can you name those test methods if you have any idea.

Components shrink, frequency increases and power/package increase also.

Package design involves electric, mechanical and thermal issues. I am not into package design, but simulation (electrical and thermal) is important to reduce time to market.

Measurement can be done with vector network analyzer and/or time domain analysers. Thermal imaging is used to assess thermal behavior. I don't know the terminology that is used within the semiconductor industry. Hopefully other people will share their experience.