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[SOLVED] sensing a signal async to clk

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emresel

emresel

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Dear friends;
Is it possible to catch a signal like attached, it is async to clk and duration might be shorter than a half period of clk.
It should be catched until next rising edge of clk and reset output again.
Do you have any synthesizable vhdl proposal circuit?

signal.GIF

Regards
 

if sygnal = '1' then
out <= '1';
elsif Clk'event and Clk = '1' then
out <= '0';
end if;
 
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    emresel

    emresel

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Thanks friends;
That helped me. But i have a few questions more. Since i am trying to learn vhdl/fpga concept myself sometimes need more expertised help. Hope you appreciate.
The code above is woking but when i change it like below, it is not synthesizable any more.

process (input, clk)
begin
if clk'event and clk = '1' then
output2 <= '0';
elsif input = '1' then
output2 <= '1';
end if;
end process;

It says "statement is not synthesizable since it does not hold its value under NOT(clock-edge) condition". Actually i can't figure out what is going wrong.
Could please explain some more on it?
Thank you

PS:I am doing this kinds of things sometimes and then stuck.
 

It says "statement is not synthesizable since it does not hold its value under NOT(clock-edge) condition". Actually i can't figure out what is going wrong.
Could please explain some more on it?
Click to expand...
The construct is not following the required syntax for aysnchronous + synchronous register action which have been previously suggested in this thread by treger. The order of statements matters.
 
Thanks,
While i am checking the net also found the note in a tutor;
The condition for synchronous actions has to be the last condition of the if structure because asynchronous control signals are usually treated with higher priority by the underlying hardware cells
Click to expand...


I think it may be noted as a general rule...
 

I think it may be noted as a general rule...
Click to expand...
Yes, you can read more about it in text books dedicated to VHDL for hardware synthesis. You can also refer to IEEE Std 1076.3, which tries to define a portable subset of synthesizable VHDL.
 
Thank you FvM;
While searching 1076.3, I found also 1076.6 which seems a useful doc.
That tells "A clock edge shall only appear in the last elsif condition." point, too.
 

Although 1076.3 is also related to synthesis, I actually meant 1076.6. Please apologize for the confusion.
 

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