Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Quite puzzling phase noise state of HMC700 phase-locked loops ?

Status
Not open for further replies.

saulbit

Member level 4
Joined
Dec 2, 2009
Messages
72
Helped
1
Reputation
2
Reaction score
1
Trophy points
1,288
Activity points
2,023
I have designed two phase locked loops, one of which is covering from 1900M~3200MHz (VCO is from Z-comm,V600ME20) and the other is for a single frequency point for 1900MHz (VCO
is from Z-comm too, V603ME) on the F4 PCB. The PLL synthesizers are both HMC700 chips. Now the pll can be locked successfully. However, when I shaked the shieding box in which the two loops are
installed, the phase noise of the two loops began to get worse and to remain the terrible phase noise after stopping the shaking. There began to be some spurs distributed about a few
hundred Hz. I have tried several ways about the reference, such as OCXO and the signal generators from agilent company,ri and I also tried different phase detector frequency, varing from
10MHz to 50MHz, and I also tried the power supplies in th DC source and the switch sources, all of which got the puzzling state described above. So would anyone could bring me some
suggestions? Any reply is welcome.
 

It could be almost anything. You could have a low frequency oscillation that needs some priming to get started, but once started goes on continuously. Does it start off clean every time you cycle the power supply, and gets noisy only after you play with it?

I would get an oscillosope probe on there and see what the power supply lines and tuning lines are doing. Maybe you need more bypass caps near the chips.

It could be an ustable PLL, so try playing with the loop parameters to make it more stable and see if the problem goes away.
 

You are getting microphony (even there is no microphone involved).
PCB layout and quality of some components can generate this phenomenon.
Use only SMD components and short layout connections to minimize stray capacitance and inductance.
V_tune tracks shall be short and far away or shielded from other signal lines, especially the reference oscillator and bus lines.
Use different power supplies for PLL and VCOs, or use a filter between, if use the same supply.
 

are you sure? All the microphony problems I have seen stop when you stop shaking it.
 

Yes, I've seen situations when microphony in PLL moved to an oscillation and I am pretty sure here is about the same situation. The most sensitive parts for this phenomenon are the components of the VCO (but I don't think here is the case because is integrated), V_tune lines and the supply lines.

I saw situation when the PLL supply LDO using a low ESR ceramic capacitor at the output, and correlated with a poor layout/grounding get this situation.
Sometimes is preferred using slightly higher ESR capacitors (aluminum or tantalum).
 

My first guess would also be to check whether the power supplies stay clean. It could be trivial: In case a large decoupling cap on a power line is not soldered perfectly, it might loose contact while shaking which puts you in a condition where the LDO might start to oscillate.

Can you stop the oscillation when heating the device (lower loop gain) or provoke it while cooling?
 

Yes, I've seen situations when microphony in PLL moved to an oscillation and I am pretty sure here is about the same situation. The most sensitive parts for this phenomenon are the components of the VCO (but I don't think here is the case because is integrated), V_tune lines and the supply lines.

I saw situation when the PLL supply LDO using a low ESR ceramic capacitor at the output, and correlated with a poor layout/grounding get this situation.
Sometimes is preferred using slightly higher ESR capacitors (aluminum or tantalum).

Some low drop out regulators are fundamentally unstable if you use a cap with too low of an ESR! They were designed with tantalum caps in mind, but lately large value ceramic caps have become available with lower cost and lower esr than the tantalums. The older LDO designs can not take it! If so, it will say it somewhere in the data sheet, like buried on page 10.
 

Thanks for everyone. I think the bug is the ground line from the DC power suppliers. I resoldered the ground line and got rid of the puzzling state. It might be a bit funny to find it for three days.
 
Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top