Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Having trouble getting Design Compiler (DC) to use my integrated clock gating cell

Status
Not open for further replies.
M

mozdzen

Newbie level 5
Joined
Mar 11, 2011
Messages
9
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,350
Hello,
I'm having trouble getting DC to use the integrated clock gating cell in DC. cell (clkgatelapoprx040)

What commands do I have to use to get it to use them?

I've tried the following:

set_scan_configuration -style multiplexed_flip_flop

propagate_constraints -gate_clock

compile_ultra -scan -gate_clock

I've also tried it without the scan option.

Am I missing some steps?

thanks,
Tom
 

Is it like DC is not able to insert any clock gating cell or it is able to insert clock gating cell but not the one which you mentioned. Ideally you should tell tool which CG cell to be inserted by using command as below:

set_clock_gating_style -pos integrated:$std_lib_name/$cg_cell_name

you can check why tool is not able to insert cell by using command "report_clock_gating -ungated -v" , it gives the reason of failure, might be your RTL is not written as to get clock gating cell.
 
I'm getting the message that it is not meeting the minimum setup time. I'm not sure what setup time it is looking for.
I did try set_clock_gating_style -pos integrated, but I didn't try specifying the specific cell yet. We have 4 different drive strengths, I suppose I can put those in brackets { } to specify multiple cells.

The RTL should be OK as we've tried this in RTL compiler and it likes the cells.

I'll see what happens when I help it out and tell it the specific cell, although I thought it would take it automatically if I said "integrated"

---------- Post added at 12:02 ---------- Previous post was at 11:07 ----------

Yes - the report gives the majority of the reason why it didn't gate the flop was due to "Enable".
Is there something I have to do to overcome this?
 

Yes DC inserts the cell automatically , but if you mention the specific CG cell you can restrict tool to do not insert higher-driving cells, but it is not mandatory.

DC checks the enable condition (enable pin is the one which decide when to gate clock) , if it passes than it inserts the CG cells. Failure is coming because tool is seeing the constant enable condition, in that situation it will not be useful to insert CG cells. Please check the RTL where DC is reporting the enable issue.

I've no experience in RTL Compiler and can't say why it did insert CG cells. Just wondering how it works, does it insert CG cells in the same way what DC does, if yes then it might be the DC tool issue.
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top